公开(公告)号：US11672130B2

公开(公告)日：2023-06-06

申请号：US17032571

申请日：2020-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonguk Kim ,  Dongsung Choi ,  Kwangmin Park ,  Jaeho Jung

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1675

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device including a first conductive line on a substrate, memory cell structures stacked on the first conductive line, a second conductive line between the memory cell structures; and a third conductive line on the memory cell structures may be provided. Each of the plurality of memory cell structures includes a data storage material pattern, a switching material pattern, and a plurality of electrode patterns, at least one of the electrode patterns includes at least one of carbon material layer or a carbon-containing material layer, and the at least one of the electrode patterns includes a first region doped with a nitrogen and a second region that is not doped with the nitrogen, or is doped with the nitrogen at a first concentration lower than a second concentration of the nitrogen in the first region.

公开(公告)号：US11094745B2

公开(公告)日：2021-08-17

申请号：US16396650

申请日：2019-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongju Kim ,  Young-Min Ko ,  Jonguk Kim ,  Kwangmin Park ,  Jeonghee Park ,  Dongsung Choi

IPC: H01L27/24 ,  H01L45/00

Abstract: A variable resistanvce memory device may include a plurality of first conductive lines extending in a first direction, a plurality of second conductive lines extending in a second direction, a plurality of memory cells, each memory cell at a respective intersection, with respect to a top down view, between a corresponding one of the first conductive lines and a corresponding one of the second conductive lines, each memory cell comprising a variable resistance structure and a switching element sandwiched between a top electrode and a bottom electrode, and a first dielectric layer filling a space between the switching elements of the memory cells. A top surface of the first dielectric layer is disposed between bottom and top surfaces of the top electrodes of the memory cells.

公开(公告)号：US11063218B2

公开(公告)日：2021-07-13

申请号：US16746258

申请日：2020-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Jung ,  Youngmin Ko ,  Jonguk Kim ,  Kwangmin Park ,  Dongsung Choi

IPC: H01L21/00 ,  H01L45/00 ,  H01L27/24

Abstract: A method of fabricating a memory device includes forming word lines and cell stacks with gaps between the cell stacks, forming a lower gap-fill insulator in the gaps, forming an upper gap-fill insulator on the lower gap-fill insulator, curing the lower gap-fill insulator and the upper gap-fill insulator to form a gap-fill insulator, and forming bit lines on the cell stacks and the gap-fill insulator. The lower gap-fill process may be performed using a first source gas that includes first and second precursors, and the upper gap-fill process may be performed using a second source gas that includes the first and second precursors, a volume ratio of the first precursor to the second precursor in the first source gas may be greater than 15:1, and a volume ratio of the first precursor to the second precursor in the second source gas may be less than 15:1.