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公开(公告)号：US20240404854A1
公开(公告)日：2024-12-05
申请号：US18633117
申请日：2024-04-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeho Jung , Yuyeon Kim , Siyeong Yang
IPC: H01L21/673 , H01L21/67
Abstract: The present disclosure relates to substrate processing apparatuses and substrate processing methods. An example substrate processing apparatus comprises an outer chamber that provides an internal space, a process tube in the outer chamber, a heater between the outer chamber and the process tube, and a boat inserted into the process tube. The boat includes a plurality of substrate support devices that are vertically stacked. Each substrate support device of the plurality of substrate support devices includes a support member that supports a substrate, a lower electrode below the support member, and an upper electrode above the support member and spaced apart from the support member.
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公开(公告)号：US11810279B2
公开(公告)日：2023-11-07
申请号：US17728535
申请日：2022-04-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeho Jung , Yeultak Sung
CPC classification number: G06T5/50 , G06T5/005 , G06T7/248 , G06T2207/20081 , G06T2207/20084 , G06T2207/20221
Abstract: Provided is an artificial intelligence (AI) system that mimics functions, such as recognition and determination by human brains, by utilizing a machine learning algorithm, such as deep learning, and applications of the AI system. An image acquisition device is disclosed including a camera configured to acquire a first image, wherein a portion of a main object is hidden from the camera by a sub-object; at least one processor configured to input the first image to a first AI neural network; detect, by the first AI neural network from data corresponding to a plurality of objects included in the first image, first data corresponding to the main object and second data corresponding to the sub-object from the first image by inputting the first image to an AI neural network, remove the sub-object from the first image, and generate, using a second AI neural network, a second image by restoring third data corresponding to at least a portion of the main object hidden by the removed sub-object by using the AI neural network, wherein the third data replaces the second data; and a display configured to display at least one of the first image and the second image.
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公开(公告)号：US20250142824A1
公开(公告)日：2025-05-01
申请号：US18794943
申请日：2024-08-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yuyeon Kim , Siyeong Yang , Chaeho Kim , Jaeho Jung
IPC: H10B43/27
Abstract: A semiconductor device includes gate electrodes on a substrate, the gate electrodes being spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate; and a memory channel structure extending through the gate electrodes in the vertical direction on the substrate. The memory channel structure may include a filling pattern extending in the vertical direction; a channel structure on a sidewall of the filling pattern and an edge portion of an upper surface of the filling pattern; a capping pattern on a central portion of the upper surface of the filling pattern and an upper surface of the channel structure; and a charge storage structure on an outer sidewall of the channel structure and a sidewall of the capping pattern.
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公开(公告)号：US11856872B2
公开(公告)日：2023-12-26
申请号：US17204599
申请日：2021-03-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaeho Jung , Kwangmin Park , Jonguk Kim , Dongsung Choi
CPC classification number: H10N70/066 , H10B63/845 , H10N70/063 , H10N70/068 , H10N70/841 , H10N70/883
Abstract: A variable resistance memory device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction and crossing the first conductive lines in a plan view, and cell structures respectively provided at crossing points of the first conductive lines and the second conductive lines in the plan view. Each of the cell structures includes a switching pattern, a variable resistance pattern, and a first electrode provided between the switching pattern and the first conductive line, the first electrode including carbon. Each of the first conductive lines includes an upper pattern including a metal nitride in an upper portion thereof. The upper pattern is in contact with a bottom surface of the first electrode.
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5.发明授权公开(公告)号：US11476419B2
公开(公告)日：2022-10-18
申请号：US16874781
申请日：2020-05-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngmin Ko , Jonguk Kim , Jaeho Jung , Dongsung Choi
Abstract: A method for manufacturing a semiconductor device includes forming a first pattern structure having a first opening on a lower structure comprising a semiconductor substrate. The first pattern structure includes a stacked pattern and a first spacer layer covering at least a side surface of the stacked pattern. A first flowable material layer including a SiOCH material is formed on the first spacer layer to fill the first opening and cover an upper portion of the first pattern structure. A first curing process including supplying a gaseous ammonia catalyst into the first flowable material layer is performed on the first flowable material layer to form a first cured material layer that includes water. A second curing process is performed on the first cured material layer to form a first low-k dielectric material layer. The first low-k dielectric material layer is planarized to form a planarized first low-k dielectric material layer.
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Patent Agency Ranking
公开(公告)号：US11411179B2
公开(公告)日：2022-08-09
申请号：US16933123
申请日：2020-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeho Jung , Kwangmin Park , Jonguk Kim , Dongsung Choi
Abstract: A method of fabricating a variable resistance memory device that includes forming a plurality of memory cells on a substrate. Each of the plurality of memory cells in a switching device and a variable resistance pattern. A capping structure is formed that commonly covers lateral side surfaces of the plurality of memory cells. An insulating gapfill layer is formed that covers the capping structure and fills a region between adjacent memory cells of the plurality of memory cells. The forming of the capping structure includes forming a second capping layer including silicon oxide that covers the lateral side surfaces of the plurality of memory cells. At least a partial portion of the second capping layer is nitrided by performing a first decoupled plasma process to form a third capping layer that includes silicon oxynitride.
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公开(公告)号：US11672130B2
公开(公告)日：2023-06-06
申请号：US17032571
申请日：2020-09-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jonguk Kim , Dongsung Choi , Kwangmin Park , Jaeho Jung
CPC classification number: H01L27/2481 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1675
Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device including a first conductive line on a substrate, memory cell structures stacked on the first conductive line, a second conductive line between the memory cell structures; and a third conductive line on the memory cell structures may be provided. Each of the plurality of memory cell structures includes a data storage material pattern, a switching material pattern, and a plurality of electrode patterns, at least one of the electrode patterns includes at least one of carbon material layer or a carbon-containing material layer, and the at least one of the electrode patterns includes a first region doped with a nitrogen and a second region that is not doped with the nitrogen, or is doped with the nitrogen at a first concentration lower than a second concentration of the nitrogen in the first region.
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公开(公告)号：US11600776B2
公开(公告)日：2023-03-07
申请号：US17033460
申请日：2020-09-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaeho Jung , Kyoung Sun Kim , Jeonghee Park , Jiho Park , Changyup Park
Abstract: An apparatus of fabricating a semiconductor device may include a chamber including a housing and a slit valve used to open or close a portion of the housing, a heater chuck provided in a lower region of the housing and used to heat a substrate, a target provided over the heater chuck, a plasma electrode provided in an upper region of the housing and used to generate plasma on the target, a heat-dissipation shield surrounding the inner wall of the housing between the plasma electrode and the heater chuck, and an edge heating structure provided between the heat-dissipation shield and the inner wall of the housing and configured to heat the heat-dissipation shield and an edge region of the substrate and to reduce a difference in temperature between center and edge regions of the substrate.
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公开(公告)号：US11063218B2
公开(公告)日：2021-07-13
申请号：US16746258
申请日：2020-01-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeho Jung , Youngmin Ko , Jonguk Kim , Kwangmin Park , Dongsung Choi
Abstract: A method of fabricating a memory device includes forming word lines and cell stacks with gaps between the cell stacks, forming a lower gap-fill insulator in the gaps, forming an upper gap-fill insulator on the lower gap-fill insulator, curing the lower gap-fill insulator and the upper gap-fill insulator to form a gap-fill insulator, and forming bit lines on the cell stacks and the gap-fill insulator. The lower gap-fill process may be performed using a first source gas that includes first and second precursors, and the upper gap-fill process may be performed using a second source gas that includes the first and second precursors, a volume ratio of the first precursor to the second precursor in the first source gas may be greater than 15:1, and a volume ratio of the first precursor to the second precursor in the second source gas may be less than 15:1.
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公开(公告)号：US10818839B2
公开(公告)日：2020-10-27
申请号：US16149507
申请日：2018-10-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaeho Jung , Kyoung Sun Kim , Jeonghee Park , Jiho Park , Changyup Park
Abstract: An apparatus of fabricating a semiconductor device may include a chamber including a housing and a slit valve used to open or close a portion of the housing, a heater chuck provided in a lower region of the housing and used to heat a substrate, a target provided over the heater chuck, a plasma electrode provided in an upper region of the housing and used to generate plasma on the target, a heat-dissipation shield surrounding the inner wall of the housing between the plasma electrode and the heater chuck, and an edge heating structure provided between the heat-dissipation shield and the inner wall of the housing and configured to heat the heat-dissipation shield and an edge region of the substrate and to reduce a difference in temperature between center and edge regions of the substrate.
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