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    SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE MATERIAL PATTERN
    1.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE MATERIAL PATTERN 有权

    公开(公告)号：US20220085105A1

    公开(公告)日：2022-03-17

    申请号：US17314638

    申请日：2021-05-07

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Jiho Park ,  Kwangmin Park ,  Wonjun Park ,  Jeonghee Park ,  Changyup Park ,  Hwasung Chae

    IPC分类号： H01L27/24 ,  H01L45/00

    摘要： A semiconductor device includes a substrate; first conductive lines extending in a first direction; second conductive lines extending in a second direction; memory cell structures between the first conductive lines and the second conductive lines; and dummy cell structures that are electrically isolated and between the first conductive lines and the second conductive lines. The memory cell structures include a data storage material pattern including a phase change material layer; and a selector material pattern overlapping the data storage material pattern in a vertical direction. The dummy cell structures include a dummy pattern including a phase change material layer. The phase change material layer of the dummy pattern includes a crystalline phase portion and an amorphous phase portion. At a cross section of the phase change material layer of the dummy pattern, an area of the crystalline phase portion is larger than an area of the amorphous phase portion.

    VARIABLE RESISTANCE MEMORY DEVICES
    2.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICES 审中-公开

    公开(公告)号：US20200052038A1

    公开(公告)日：2020-02-13

    申请号：US16277385

    申请日：2019-02-15

    申请人： Samsung Electronics Co., Ltd.

    发明人： Byongju Kim ,  Young-min Ko ,  Jong-uk Kim ,  Kwangmin Park ,  Jeong-hee Park

    IPC分类号： H01L27/24 ,  H01L45/00

    摘要： There is provided a variable resistance memory device including a first electrode line layer including first electrode lines extending in a first direction and spaced apart from each other on a substrate, a second electrode line layer that is above the first electrode line layer and including second electrode lines extending in a second direction orthogonal to the first direction and spaced apart from each other, and a memory cell layer including memory cells between the first electrode line layer and the second electrode line layer. Each of the memory cells includes a selection device layer, an intermediate electrode layer, and a variable resistance layer. A first insulating layer is between the first electrode lines, a second insulating layer is between the memory cells, and a third insulating layer is between the second electrode lines. The second insulating layer includes air gaps on side surfaces of the memory cells.

    Three-dimensional semiconductor memory devices and methods of fabricating the same
    4.
    发明授权
    Three-dimensional semiconductor memory devices and methods of fabricating the same 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US09202819B2

    公开(公告)日：2015-12-01

    申请号：US14493849

    申请日：2014-09-23

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Juyul Lee ,  Bumsu Kim ,  Kwangmin Park ,  Hyun Park ,  Jae-young Ahn ,  Dongchul Yoo ,  Jongsik Chun ,  Kihyun Hwang

    IPC分类号： H01L27/105 ,  H01L27/115 ,  H01L29/792

    CPC分类号： H01L27/11582 ,  H01L27/1052 ,  H01L29/7926

    摘要： A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer.

    摘要翻译： 三维（3D）半导体存储器件包括电极分离图案，堆叠结构，数据存储层和沟道结构。 电极分离图案设置在基板上。 堆叠结构设置在电极分离图案的侧壁上。 堆叠结构包括与电极分离图案的侧壁相对的波纹状侧壁。 电极分离图案的侧壁垂直于基板。 数据存储层设置在波纹侧壁上。 通道结构设置在电荷存储层上。

    Variable resistance memory device and method of fabricating the same
    8.
    发明授权
    Variable resistance memory device and method of fabricating the same 有权

    公开(公告)号：US11411179B2

    公开(公告)日：2022-08-09

    申请号：US16933123

    申请日：2020-07-20

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Jaeho Jung ,  Kwangmin Park ,  Jonguk Kim ,  Dongsung Choi

    IPC分类号： H01L45/00 ,  H01L27/24

    摘要： A method of fabricating a variable resistance memory device that includes forming a plurality of memory cells on a substrate. Each of the plurality of memory cells in a switching device and a variable resistance pattern. A capping structure is formed that commonly covers lateral side surfaces of the plurality of memory cells. An insulating gapfill layer is formed that covers the capping structure and fills a region between adjacent memory cells of the plurality of memory cells. The forming of the capping structure includes forming a second capping layer including silicon oxide that covers the lateral side surfaces of the plurality of memory cells. At least a partial portion of the second capping layer is nitrided by performing a first decoupled plasma process to form a third capping layer that includes silicon oxynitride.

    Variable resistance memory devices
    10.
    发明授权
    Variable resistance memory devices 有权

    公开(公告)号：US10720470B2

    公开(公告)日：2020-07-21

    申请号：US16277385

    申请日：2019-02-15

    申请人： Samsung Electronics Co., Ltd.

    发明人： Byongju Kim ,  Young-min Ko ,  Jong-uk Kim ,  Kwangmin Park ,  Jeong-hee Park

    IPC分类号： H01L27/24 ,  H01L45/00 ,  H01F10/32 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10

    摘要： There is provided a variable resistance memory device including a first electrode line layer including first electrode lines extending in a first direction and spaced apart from each other on a substrate, a second electrode line layer that is above the first electrode line layer and including second electrode lines extending in a second direction orthogonal to the first direction and spaced apart from each other, and a memory cell layer including memory cells between the first electrode line layer and the second electrode line layer. Each of the memory cells includes a selection device layer, an intermediate electrode layer, and a variable resistance layer. A first insulating layer is between the first electrode lines, a second insulating layer is between the memory cells, and a third insulating layer is between the second electrode lines. The second insulating layer includes air gaps on side surfaces of the memory cells.