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公开(公告)号：US10930848B2
公开(公告)日：2021-02-23
申请号：US16415424
申请日：2019-05-17
发明人： Byongju Kim , Young-Min Ko , Jonguk Kim , Jaeho Jung , Dongsung Choi
摘要： A method of manufacturing a variable resistance memory device includes: forming an array of memory cells on a substrate, each memory cell including a variable resistance structure and a switching element; and forming a sidewall insulating layer covering a sidewall of the switching element. The forming the sidewall insulating layer includes: a preliminary step of supplying a silicon source to an exposed sidewall of the switching element; and a main step of performing a process cycle a plurality of times, the process cycle comprising supplying the silicon source and supplying a reaction gas, A time duration of the supplying the silicon source in the preliminary step is longer than a time duration of the supplying the silicon gas in the process cycle in the main step.
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公开(公告)号：US10720470B2
公开(公告)日：2020-07-21
申请号：US16277385
申请日：2019-02-15
发明人： Byongju Kim , Young-min Ko , Jong-uk Kim , Kwangmin Park , Jeong-hee Park
摘要： There is provided a variable resistance memory device including a first electrode line layer including first electrode lines extending in a first direction and spaced apart from each other on a substrate, a second electrode line layer that is above the first electrode line layer and including second electrode lines extending in a second direction orthogonal to the first direction and spaced apart from each other, and a memory cell layer including memory cells between the first electrode line layer and the second electrode line layer. Each of the memory cells includes a selection device layer, an intermediate electrode layer, and a variable resistance layer. A first insulating layer is between the first electrode lines, a second insulating layer is between the memory cells, and a third insulating layer is between the second electrode lines. The second insulating layer includes air gaps on side surfaces of the memory cells.
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公开(公告)号：US20240147722A1
公开(公告)日：2024-05-02
申请号：US18331397
申请日：2023-06-08
发明人： Byongju Kim , Dongsung Choi , Wonjun Park , Donghwa Lee , Jaemin Jung , Changheon Cheon
IPC分类号： H10B43/27 , H01L23/528 , H01L25/065 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/35 , H10B80/00
CPC分类号： H10B43/27 , H01L23/5283 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/35 , H10B80/00 , H01L2225/06551
摘要： A semiconductor device may include a gate stack that includes a first insulating pattern, a second insulating pattern adjacent to the first insulating pattern, a third insulating pattern adjacent to the second insulating pattern, a first conductive pattern between the first and second insulating patterns, and a second conductive pattern between the second and third insulating patterns, a channel layer that extends in the gate stack, a tunnel insulating layer on the channel layer, and a first data storage pattern and a second data storage pattern on the tunnel insulating layer. The first data storage pattern may include a first outer portion between the first and second insulating patterns, and a first inner portion on the first outer portion.
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公开(公告)号：US11094745B2
公开(公告)日：2021-08-17
申请号：US16396650
申请日：2019-04-27
发明人： Byongju Kim , Young-Min Ko , Jonguk Kim , Kwangmin Park , Jeonghee Park , Dongsung Choi
摘要： A variable resistanvce memory device may include a plurality of first conductive lines extending in a first direction, a plurality of second conductive lines extending in a second direction, a plurality of memory cells, each memory cell at a respective intersection, with respect to a top down view, between a corresponding one of the first conductive lines and a corresponding one of the second conductive lines, each memory cell comprising a variable resistance structure and a switching element sandwiched between a top electrode and a bottom electrode, and a first dielectric layer filling a space between the switching elements of the memory cells. A top surface of the first dielectric layer is disposed between bottom and top surfaces of the top electrodes of the memory cells.
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公开(公告)号：US20240224523A1
公开(公告)日：2024-07-04
申请号：US18493853
申请日：2023-10-25
发明人： Dongsung Choi , Byongju Kim , Wonjun Park , Jaemin Jung , Changheon Cheon
摘要： A non-volatile memory device includes a substrate, a mold structure including a plurality of gate electrodes and a plurality of mold insulating layers, wherein the plurality of gate electrodes are stacked in a step shape, a channel structure that extends through the mold structure, and a cell contact that extends through the mold structure, the cell contact is connected to a first gate electrode, and the cell contact is not electrically connected to a second gate electrode among the plurality of gate electrodes, wherein the first gate electrode includes: an extension portion; a pad portion having a vertical thickness greater than a vertical thickness of the extension portion; and a connection portion that electrically connects the pad portion to the cell contact, the connection portion has a vertical thickness less than a vertical thickness of the pad portion, and one or more first insulating rings on the connection portion.
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公开(公告)号：US20240206180A1
公开(公告)日：2024-06-20
申请号：US18341066
申请日：2023-06-26
发明人： Dongsung Choi , Byongju Kim , Youjung Kim , Chaeho Kim , Changheon Cheon
IPC分类号： H01L29/792
摘要： A vertical non-volatile memory device may include a mold structure including first and second insulation patterns and a first gate electrode, a semiconductor pattern extending through the mold structure in a first direction, a first charge insulation layer between the first insulation pattern and the semiconductor pattern, a second charge insulation layer spaced apart from the first charge insulation layer and between the second insulation pattern and the semiconductor pattern, a charge storage layer between the first and second charge insulation layers and between the first gate electrode and the semiconductor pattern, and a first blocking insulation layer between the first gate electrode and the charge storage layer, and a first length in the first direction of the first gate electrode is shorter than a second length in the first direction of a first surface of the charge storage layer which is in contact with the first blocking insulation layer.
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公开(公告)号：US20240074195A1
公开(公告)日：2024-02-29
申请号：US18308262
申请日：2023-04-27
发明人： Byongju Kim , Dongsung Choi , Wonjun Park , Donghwa Lee , Jaemin Jung , Changheon Cheon
摘要： A semiconductor device includes a conductive pattern, an insulating pattern, a channel film extending in a vertical direction inside a channel hole, a charge trap pattern between the conductive pattern and the channel film inside the channel hole, a tunneling dielectric film between the charge trap pattern and the channel film, and a blocking dielectric film extending between the conductive pattern and the charge trap pattern and between the insulating pattern and the tunneling dielectric film. The insulating pattern includes a first insulating pattern overlapping the conductive pattern in the vertical direction and a second insulating pattern protruding in the lateral direction from the first insulating pattern into the channel hole and toward the channel film. The first insulating pattern has a first dielectric constant, and the second insulating pattern has a second dielectric constant that is lower than the first dielectric constant.
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公开(公告)号：US11456414B2
公开(公告)日：2022-09-27
申请号：US16416472
申请日：2019-05-20
发明人： Jonguk Kim , Young-Min Ko , Byongju Kim , Jaeho Jung , Dongsung Choi
摘要： A method of manufacturing a variable resistance memory device may include: forming a memory cell including a variable resistance pattern on a substrate; performing a first process to deposit a first protective layer covering the memory cell; and performing a second process to deposit a second protective layer on the first protective layer. The first process and the second process may use the same source material and the same nitrogen reaction material, and a nitrogen content in the first protective layer may be less than a nitrogen content in the second protective layer.
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公开(公告)号：US20200052038A1
公开(公告)日：2020-02-13
申请号：US16277385
申请日：2019-02-15
发明人： Byongju Kim , Young-min Ko , Jong-uk Kim , Kwangmin Park , Jeong-hee Park
摘要： There is provided a variable resistance memory device including a first electrode line layer including first electrode lines extending in a first direction and spaced apart from each other on a substrate, a second electrode line layer that is above the first electrode line layer and including second electrode lines extending in a second direction orthogonal to the first direction and spaced apart from each other, and a memory cell layer including memory cells between the first electrode line layer and the second electrode line layer. Each of the memory cells includes a selection device layer, an intermediate electrode layer, and a variable resistance layer. A first insulating layer is between the first electrode lines, a second insulating layer is between the memory cells, and a third insulating layer is between the second electrode lines. The second insulating layer includes air gaps on side surfaces of the memory cells.
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