公开(公告)号：US20220336338A1

公开(公告)日：2022-10-20

申请号：US17857696

申请日：2022-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun KIM

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/18

Abstract: Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.

公开(公告)号：US20200091066A1

公开(公告)日：2020-03-19

申请号：US16351709

申请日：2019-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun KIM ,  Seokhyun LEE ,  Minjun BAE

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: A redistribution subtrate, a method of fabricating the same, and a semiconductor package are provided. The method including forming a first conductive pattern; forming a first photosensitive layer on the first conductive pattern, the first photosensitive layer having a first through hole exposing a first portion of the first conductive pattern; forming a first via in the first through hole; removing the first photosensitive layer; forming a first dielectric layer that encapsulates the first conductive pattern and the first via, the first dielectric layer exposing a top surface of the first via; and forming a second conductive pattern on the top surface of the first via.

公开(公告)号：US20250149418A1

公开(公告)日：2025-05-08

申请号：US19013244

申请日：2025-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun KIM ,  Minjun BAE ,  Hyeonseok LEE ,  Gwangjae JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L25/18

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

公开(公告)号：US20230187345A1

公开(公告)日：2023-06-15

申请号：US18105945

申请日：2023-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun KIM ,  Seokhyun Lee ,  Minjun Bae

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L24/09 ,  H01L24/17 ,  H01L23/3128 ,  H01L23/5283 ,  H01L21/565 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76819 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/0231 ,  H01L2224/02373

Abstract: A method is provided and includes forming a first conductive pattern; forming a photosensitive layer on the first conductive pattern, the photosensitive layer having a first through hole exposing a portion of the first conductive pattern; forming a first via in the first through hole; removing the photosensitive layer; forming a dielectric layer encapsulating the first conductive pattern and the first via, the dielectric layer exposing a top surface of the first via; forming a second conductive pattern on the top surface of the first via, forming a dielectric layer covering the second conductive pattern; etching the dielectric layer to form a second through hole that exposes a portion of the second conductive pattern; forming a second via filling the second through hole and an under bump pad on the second via; and mounting a semiconductor chip on the under bump pad using a connection terminal.

公开(公告)号：US20230069490A1

公开(公告)日：2023-03-02

申请号：US17723981

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonseok LEE ,  Jongyoun KIM ,  Seokhyun LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces, a first semiconductor chip on the first surface, external terminals on the second surface, a second semiconductor chip above the first semiconductor chip, external connection members below the second semiconductor chip, conductive pillars electrically connecting the external connection members to the redistribution substrate. The second semiconductor chip includes a device layer, a wiring layer, and a redistribution layer on a semiconductor substrate. The wiring layer includes intermetallic dielectric layers, wiring lines, and a conductive pad connected to an uppermost wiring line. The redistribution layer includes a first redistribution dielectric layer, a first redistribution pattern, and a second redistribution dielectric layer. A vertical distance between the semiconductor substrate and the conductive pillars is less than that between the first semiconductor chip and the external terminals.

公开(公告)号：US20220367402A1

公开(公告)日：2022-11-17

申请号：US17648425

申请日：2022-01-20

Applicant: Samsung Electronics Co., Ltd

Inventor： INHYUNG SONG ,  Seokhyun LEE ,  Jongyoun KIM

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a base substrate; a redistribution substrate disposed on the base substrate, and that includes first insulating layers and redistribution pattern layers disposed on the first insulating layers, respectively; a semiconductor chip disposed on the redistribution substrate and electrically connected to the redistribution pattern layers; and a chip structure disposed on the redistribution substrate adjacent to the semiconductor chip and electrically connected to the semiconductor chip through the redistribution pattern layers, wherein the semiconductor chip includes a body that has an active surface that faces the redistribution substrate; first and second contact pads spaced apart from each other below the active surface; a first bump structure and a passive device electrically connected to the first connection pad at a lower level from the first connection pad; and a second bump structure electrically connected to the second connection pad at a lower level from the second connection pad.

公开(公告)号：US20220310496A1

公开(公告)日：2022-09-29

申请号：US17509224

申请日：2021-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun KIM ,  Minjun BAE ,  Hyeonseok LEE ,  Gwangjae JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

公开(公告)号：US20210111114A1

公开(公告)日：2021-04-15

申请号：US16884212

申请日：2020-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun LEE ,  Jongyoun KIM ,  Yeonho JANG ,  Jaegwon JANG

IPC: H01L23/498 ,  H01L21/48

Abstract: A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.

公开(公告)号：US20200098716A1

公开(公告)日：2020-03-26

申请号：US16698117

申请日：2019-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn Ji MIN ,  Seokhyun LEE ,  Jongyoun KIM ,  Kyoung Lim SUK ,  SeokWon LEE

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

Abstract: A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the second opening at least partially exposes the chip pad, wherein, inside the second insulating layer, the first barrier metal layer is in contact with the chip pad through the second opening, and wherein the first redistribution conductive pattern has a surface roughness including protrusions extending in a range of from about 0.01 μm to about 0.5 μm, and the first insulating layer has a surface roughness smaller than the surface roughness of the first redistribution conductive pattern.

公开(公告)号：US20250096158A1

公开(公告)日：2025-03-20

申请号：US18966367

申请日：2024-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun KIM

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538

Abstract: A semiconductor package includes a semiconductor chip, a redistribution insulating layer having a first opening, and an external connection bump including a first portion filling the first opening. A lower bump pad includes a first surface and a second surface opposite the first surface. The first surface includes a contact portion that directly contacts the first portion of the external connection bump and a cover portion surrounding side surfaces of the contact portion. A first conductive barrier layer surrounds side surfaces of the lower bump pad and is disposed between the lower bump pad and the redistribution insulating layer. A redistribution pattern directly contacts the second surface of the lower bump pad and is configured to electrically connect the lower bump pad to the semiconductor chip.