公开(公告)号：US20240363486A1

公开(公告)日：2024-10-31

申请号：US18771548

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yuan Sheng Chiu ,  Chih-Kai Cheng ,  Tsung-Shu Lin

IPC: H01L23/40 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/4006 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/94 ,  H01L2023/405 ,  H01L2023/4087 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/26155 ,  H01L2224/83897

Abstract: In an embodiment, a device includes: an integrated circuit die; a redistribution structure over a front-side surface of the integrated circuit die; a socket over the redistribution structure; a mechanical brace over the socket, the mechanical brace having an opening exposing the socket, edge regions of the socket overlapping edge regions of the mechanical brace at the opening; a first standoff screw disposed in the edge regions of the mechanical brace, the first standoff screw physically contacting the socket, the first standoff screw extending a first distance between the socket and the mechanical brace; and a bolt extending through the mechanical brace and the redistribution structure.

公开(公告)号：US20240321730A1

公开(公告)日：2024-09-26

申请号：US18189673

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Hsiao-Tsung YEN ,  Xingyi HUA ,  Jeongil Jay KIM

IPC: H01L23/522

CPC classification number: H01L23/5227 ,  H01L28/10 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0231 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/2105

Abstract: An integrated device comprising a die substrate, a die interconnection portion coupled to the die substrate, and a stacked inductor that includes a first figure 8-shaped inductor and a second figure 8-shaped inductor. The stacked inductor may include a first spiral comprising a first origin and a first tail, a second spiral comprising a second origin and a second tail, a third spiral comprising a third origin and a third tail and a fourth spiral comprising a fourth origin and a fourth tail. The first spiral, the second spiral, the third spiral and the fourth spiral may form the first figure 8-shaped inductor and the second figure 8-shaped inductor. The stacked inductor may be located in the die interconnection.

公开(公告)号：US12087717B2

公开(公告)日：2024-09-10

申请号：US17369292

申请日：2021-07-07

Applicant: Infineon Technologies Austria AG

Inventor： Thomas Feil ,  Danny Clavette ,  Paul Ganitzer ,  Martin Poelzl ,  Carsten von Koblinski

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/538 ,  H01L25/07 ,  H01L25/16 ,  H01L27/088

CPC classification number: H01L24/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/072 ,  H01L25/16 ,  H01L27/088 ,  H01L23/3107 ,  H01L24/48 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02381 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/08137 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/245 ,  H01L2224/2518 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73227 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/245 ,  H01L2924/01029 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/13055 ,  H01L2924/00

Abstract: In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.

公开(公告)号：US12080623B2

公开(公告)日：2024-09-03

申请号：US17322191

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yuan Sheng Chiu ,  Chih-Kai Cheng ,  Tsung-Shu Lin

IPC: H01L23/40 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/4006 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/94 ,  H01L2023/405 ,  H01L2023/4087 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/26155 ,  H01L2224/83897

Abstract: In an embodiment, a device includes: an integrated circuit die; a redistribution structure over a front-side surface of the integrated circuit die; a socket over the redistribution structure; a mechanical brace over the socket, the mechanical brace having an opening exposing the socket, edge regions of the socket overlapping edge regions of the mechanical brace at the opening; a first standoff screw disposed in the edge regions of the mechanical brace, the first standoff screw physically contacting the socket, the first standoff screw extending a first distance between the socket and the mechanical brace; and a bolt extending through the mechanical brace and the redistribution structure.

公开(公告)号：US20240274590A1

公开(公告)日：2024-08-15

申请号：US18648917

申请日：2024-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hung-Yi Kuo ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Tsung-Yuan Yu ,  Ming Hung Tseng

IPC: H01L25/00 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L22/14 ,  H01L22/32 ,  H01L24/03 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.

公开(公告)号：US12057417B2

公开(公告)日：2024-08-06

申请号：US16739578

申请日：2020-01-10

Applicant: Texas Instruments Incorporated

Inventor： Masamitsu Matsuura ,  Daiki Komatsu

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L23/3114 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/11013 ,  H01L2224/11334

Abstract: A wafer chip-scale package (WCSP) includes a substrate including a semiconductor surface layer including circuitry configured for at least one function having at least a top metal interconnect layer thereon that includes at least one bond pad coupled to a node in the circuitry. A redistribution layer (RDL) including a bump pad is coupled by a trace to metal filled plugs through a passivation layer to the bond pad. A solder ball is on the bump pad, and a dielectric ring is on the bump pad that has an inner area that is in physical contact with the solder ball.

公开(公告)号：US12051684B2

公开(公告)日：2024-07-30

申请号：US18241592

申请日：2023-09-01

Applicant: Micron Technology, Inc.

Inventor： Jong Sik Paek ,  Yeongbeom Ko

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/50 ,  H01L23/49827 ,  H01L2224/02122 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207

Abstract: Semiconductor device assemblies can include a substrate having a substrate contact. The assemblies can include a first semiconductor device and a second semiconductor device arranged in a face-to-face configuration. The assemblies can include a fan-out porch on the substrate at a lateral side of the first semiconductor device and including a wirebond contact, the wirebond contact being electrically coupled to the first semiconductor device. The assemblies can include a wirebond operably coupling the wirebond contact to the substrate contact. The assemblies can include a pillar or bump operably coupling the active side of the first semiconductor device to the active side of the second semiconductor device. In some embodiments, the wirebond contact is operably couple to the active side of the first semiconductor device.

公开(公告)号：US12021046B2

公开(公告)日：2024-06-25

申请号：US17944983

申请日：2022-09-14

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Paolo Colpani ,  Samuele Sciarrillo ,  Ivan Venegoni ,  Francesco Maria Pipia ,  Simone Bossi ,  Carmela Cupeta

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L24/03 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L24/05 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03464 ,  H01L2224/03614 ,  H01L2224/04042 ,  H01L2224/05024 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05664 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/0132 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107

Abstract: A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

公开(公告)号：US12009256B2

公开(公告)日：2024-06-11

申请号：US18338095

申请日：2023-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chin Wei Kang ,  Yung-Han Chuang ,  Lung-Kai Mao ,  Yung-Sheng Lin

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76852 ,  H01L21/76871 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

公开(公告)号：US20240178102A1

公开(公告)日：2024-05-30

申请号：US18304638

申请日：2023-04-21

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Chun-Ti LU ,  Hao-Yi TSAI ,  Chiahung LIU ,  Ken-Yu CHANG ,  Tzuan-Horng LIU ,  Chih-Hao CHANG ,  Bo-Jiun LIN ,  Shih-Wei CHEN ,  Pei-Rong NI ,  Hsin-Wei HUANG ,  Zheng GangTsai ,  Tai-You LIU ,  Steve SHIH ,  Yu-Ting HUANG ,  Steven SONG ,  Yu-Ching WANG ,  Tsung-Yuan YU ,  Hung-Yi KUO ,  CHung-Shi LIU ,  Tsung-Hsien CHIANG ,  Ming Hung TSENG ,  Yen-Liang LIN ,  Tzu-Sung HUANG ,  Chun-Chih CHUANG

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/13111 ,  H01L2224/48227 ,  H01L2924/1436

Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.