公开(公告)号：US20220310496A1

公开(公告)日：2022-09-29

申请号：US17509224

申请日：2021-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun KIM ,  Minjun BAE ,  Hyeonseok LEE ,  Gwangjae JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

公开(公告)号：US20230025903A1

公开(公告)日：2023-01-26

申请号：US17714490

申请日：2022-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun KIM ,  Minjung KIM ,  Gwangjae JEON

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package according to the disclosure includes a terminal, a conductive pattern connected to the terminal, a barrier layer covering a top surface and a first side wall of the conductive pattern, an insulating layer surrounding the barrier layer, a protection layer covering a bottom surface of the insulating layer and a bottom surface of the barrier layer, a redistribution pattern connected to the barrier layer, a semiconductor chip electrically connected to the redistribution pattern, and a molding layer surrounding the semiconductor chip. A top surface of the protection layer includes a first portion contacting the conductive pattern, and a second portion contacting the barrier layer.

公开(公告)号：US20220077066A1

公开(公告)日：2022-03-10

申请号：US17215517

申请日：2021-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun KIM ,  Seokhyun LEE ,  Gwangjae JEON

IPC: H01L23/538 ,  H01L23/00

Abstract: A semiconductor package includes a redistribution substrate having a semiconductor chip mounted on a top surface thereof with and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate includes a first redistribution pattern on a bottom surface of the connection terminal and comprising a first via and a first interconnection on the first via, a pad pattern between the first redistribution pattern and the connection terminal and comprising a pad via and a pad on the pad via, and a second redistribution pattern between the first redistribution pattern and the pad pattern and comprising a second via and a second interconnection on the second via with a recess region where a portion of a top surface of the second interconnection is recessed. A bottom surface of the recess region is located at a lower level than a topmost surface of the second interconnection.

公开(公告)号：US20240203850A1

公开(公告)日：2024-06-20

申请号：US18588699

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun KIM ,  Minjun BAE ,  Hyeonseok LEE ,  Gwangjae JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L25/18

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/18 ,  H01L23/34 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/73204

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

公开(公告)号：US20220077041A1

公开(公告)日：2022-03-10

申请号：US17405603

申请日：2021-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gwangjae JEON ,  Jung-Ho PARK ,  Seokhyun LEE ,  Yaejung YOON

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.

公开(公告)号：US20230141447A1

公开(公告)日：2023-05-11

申请号：US17896638

申请日：2022-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonil LEE ,  Minki KIM ,  Jihoon KIM ,  Gwangjae JEON

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L24/08 ,  H01L24/03 ,  H01L24/80 ,  H01L24/97 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L24/16 ,  H01L2224/95001 ,  H01L2224/03616 ,  H01L2224/80204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/35121 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05541 ,  H01L2224/05555 ,  H01L2224/05015 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/05687 ,  H01L2224/05647 ,  H01L2224/05166 ,  H01L2224/05187

Abstract: A semiconductor package is provided in which a first insulating layer includes a first recess spaced apart from a first pad in a first direction, and a second insulating layer includes a second recess spaced apart from a second pad in the first direction and overlapping at least a portion of the first recess in a second direction, perpendicular to the first direction, to provide an air gap together with the first recess. The semiconductor package further includes a first bonding surface defined by the first and second insulating layers contacting each other on one side of the air gap, adjacent to the first and second pads, and a second bonding surface defined by the first and second insulating layers contacting each other on another side of the air gap, opposite to the one side.

公开(公告)号：US20210020600A1

公开(公告)日：2021-01-21

申请号：US16748138

申请日：2020-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonho JANG ,  Gwangjae JEON ,  Dongkyu KIM ,  Jungho PARK ,  Seokhyun LEE

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/78

Abstract: Provided is a method of manufacturing a semiconductor package including providing a carrier substrate, providing sacrificial layer on the carrier substrate, the sacrificial layer including a first sacrificial layer and a second sacrificial layer, providing a redistribution wiring layer on the sacrificial layer, providing a plurality of semiconductor chips on the redistribution wiring layer, providing a mold layer provided on the sacrificial layer, the redistribution wiring layer, and the plurality of semiconductor chips, detaching the first sacrificial layer from the second sacrificial layer, and dicing the second sacrificial layer, the redistribution wiring layer, and the mold layer, wherein a diameters of the first sacrificial layer and the second sacrificial layer are respectively less than a diameter of the carrier substrate, and a diameter of the mold layer is greater than the diameter of the redistribution wiring layer and less than the diameter of the first sacrificial layer.