公开(公告)号：US20220013502A1

公开(公告)日：2022-01-13

申请号：US17194575

申请日：2021-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuha Lee ,  Joohee Jang ,  Seokho Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Seongmin Son ,  Yikoan Hong

IPC: H01L25/065 ,  H01L23/538

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, first main connection pad structures, and first dummy connection pad structures. The first main connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip and arranged to be apart from each other by a first main pitch in a first direction parallel to a top surface of the first semiconductor chip, wherein each of the first main connection pad structures includes a first connection pad electrically connected to the first semiconductor chip, and a second connection pad electrically connected to the second semiconductor chip and contacting the first connection pad. The first dummy connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip, are arranged to be apart from the first main connection pad structures, and are arranged to be apart from each other by a first dummy pitch in the first direction, the first dummy pitch being greater than the first main pitch.

公开(公告)号：US20210066224A1

公开(公告)日：2021-03-04

申请号：US16831331

申请日：2020-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee Jang ,  Seokho Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Kyuha Lee

IPC: H01L23/00 ,  H01L27/146

Abstract: A semiconductor device is provided and includes first and second semiconductor chips bonded together. The first chip includes a first substrate, a first insulating layer disposed on the first substrate and having a top surface, a first metal pad embedded in the first insulating layer and having a top surface substantially planar with the top surface of the first insulating layer, and a first barrier disposed between the first insulating layer and the first metal pad. The second chip includes a second substrate, a second insulating layer, a second metal pad, and a second barrier with a similar configuration to the first chip. The top surfaces of the first and second insulating layers are bonded to provide a bonding interface, the first and second metal pads are connected, and a portion of the first insulating layer is in contact with a side region of the first metal pad.