公开(公告)号：US20220037273A1

公开(公告)日：2022-02-03

申请号：US17206337

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyung Park ,  Seokho Kim ,  Hoonjoo Na ,  Seongmin Son ,  Kyuha Lee ,  Yikoan Hong

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures.

公开(公告)号：US11887841B2

公开(公告)日：2024-01-30

申请号：US17194575

申请日：2021-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuha Lee ,  Joohee Jang ,  Seokho Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Seongmin Son ,  Yikoan Hong

IPC: H01L25/065 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, first main connection pad structures, and first dummy connection pad structures. The first main connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip and arranged to be apart from each other by a first main pitch in a first direction parallel to a top surface of the first semiconductor chip, wherein each of the first main connection pad structures includes a first connection pad electrically connected to the first semiconductor chip, and a second connection pad electrically connected to the second semiconductor chip and contacting the first connection pad. The first dummy connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip, are arranged to be apart from the first main connection pad structures, and are arranged to be apart from each other by a first dummy pitch in the first direction, the first dummy pitch being greater than the first main pitch.

公开(公告)号：US20210066250A1

公开(公告)日：2021-03-04

申请号：US16855352

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuha Lee ,  Pilkyu Kang ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Jaehyung Park ,  Joohee Jang ,  Yikoan Hong

IPC: H01L25/065 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor device according to example embodiments includes: sequentially forming first through third insulating layers on a substrate; forming an opening by etching the first through third insulating layers; forming a conductive layer configured in the opening; forming a fourth insulating layer in the opening after the forming of the conductive layer; and removing a portion of an edge region of the substrate after the forming of the fourth insulating layer.

公开(公告)号：US20240243102A1

公开(公告)日：2024-07-18

申请号：US18410644

申请日：2024-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yikoan Hong ,  Seokho Kim ,  Kwangjin Moon

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/544 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/544 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H10B80/00 ,  H01L24/08 ,  H01L2223/5446 ,  H01L2224/08225 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1811

Abstract: Provided is a semiconductor package including a first semiconductor chip, at least one second semiconductor chip on a top surface of the first semiconductor chip, a molding layer on the at least one second semiconductor chip, and a marking layer on at least one side of the molding layer, the marking layer including a hydrophobic material, wherein inner sidewalls of the marking layer contact a lower portion of sidewalls of the molding layer.

公开(公告)号：US11362067B2

公开(公告)日：2022-06-14

申请号：US16855352

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuha Lee ,  Pilkyu Kang ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Jaehyung Park ,  Joohee Jang ,  Yikoan Hong

IPC: H01L25/065 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor device according to example embodiments includes: sequentially forming first through third insulating layers on a substrate; forming an opening by etching the first through third insulating layers; forming a conductive layer configured in the opening; forming a fourth insulating layer in the opening after the forming of the conductive layer; and removing a portion of an edge region of the substrate after the forming of the fourth insulating layer.

公开(公告)号：US11658139B2

公开(公告)日：2023-05-23

申请号：US17206337

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyung Park ,  Seokho Kim ,  Hoonjoo Na ,  Seongmin Son ,  Kyuha Lee ,  Yikoan Hong

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/06 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05176 ,  H01L2224/05554 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05649 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06177 ,  H01L2224/06505 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/32145

Abstract: A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures.

公开(公告)号：US20220013502A1

公开(公告)日：2022-01-13

申请号：US17194575

申请日：2021-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuha Lee ,  Joohee Jang ,  Seokho Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Seongmin Son ,  Yikoan Hong

IPC: H01L25/065 ,  H01L23/538

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, first main connection pad structures, and first dummy connection pad structures. The first main connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip and arranged to be apart from each other by a first main pitch in a first direction parallel to a top surface of the first semiconductor chip, wherein each of the first main connection pad structures includes a first connection pad electrically connected to the first semiconductor chip, and a second connection pad electrically connected to the second semiconductor chip and contacting the first connection pad. The first dummy connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip, are arranged to be apart from the first main connection pad structures, and are arranged to be apart from each other by a first dummy pitch in the first direction, the first dummy pitch being greater than the first main pitch.