公开(公告)号：US12021080B2

公开(公告)日：2024-06-25

申请号：US18353214

申请日：2023-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo Lee ,  Wonkeun Chung ,  Hoonjoo Na ,  Suyoung Bae ,  Jaeyeol Song ,  Jonghan Lee ,  HyungSuk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/823842 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78696

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US11824035B2

公开(公告)日：2023-11-21

申请号：US17826756

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyung Park ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Kyuha Lee ,  Joohee Jang

IPC: H01L23/00 ,  H10K19/20 ,  H10K39/32 ,  H01L27/146

CPC classification number: H01L24/32 ,  H01L24/83 ,  H10K19/20 ,  H10K39/32 ,  H01L27/14647 ,  H01L2224/32145 ,  H01L2224/32501 ,  H01L2224/83359 ,  H01L2224/83895 ,  H01L2224/83896

Abstract: A semiconductor device includes a first adsorption layer, a first bonding layer, a second bonding layer, and a second adsorption layer stacked on a first substrate, and a conductive pattern structure penetrating through the first adsorption layer, the first bonding layer, the second bonding layer and the second adsorption layer. The first and second bonding layers are in contact with each other, and each of the first and second adsorption layers includes a low-κ dielectric material.

公开(公告)号：US11749586B2

公开(公告)日：2023-09-05

申请号：US17514218

申请日：2021-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sonkwan Hwang ,  Taeseong Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Hyungjun Jeon

IPC: H01L21/00 ,  H01L23/48 ,  H01L27/088 ,  H01L25/065 ,  H01L21/768 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L25/0657 ,  H01L27/0886 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.

公开(公告)号：US11728197B2

公开(公告)日：2023-08-15

申请号：US17218606

申请日：2021-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyun Phee ,  Hoechul Kim ,  Seokho Kim ,  Taeyeong Kim ,  Hoonjoo Na

IPC: H01L21/68 ,  H01L21/67 ,  H01L21/683

CPC classification number: H01L21/681 ,  H01L21/67092 ,  H01L21/6838

Abstract: A wafer bonding apparatus including a first stage having a first surface and being configured to hold a first wafer on the first surface; a second stage having a second surface and being configured to hold a second wafer on the second surface facing the first surface; a first target image sensor on an outer portion of the first stage; a second target image sensor on an outer portion of the second stage; and a target portion on the first or second stage, the target portion having a target plate fixedly installed and spaced apart from the first or second target image sensor by a predetermined distance, wherein, in an alignment measurement of the first and second stages, the first and second stages are movable so that the first and second target image sensors face each other and the target plate is between the first and second target image sensors.

公开(公告)号：US11658139B2

公开(公告)日：2023-05-23

申请号：US17206337

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyung Park ,  Seokho Kim ,  Hoonjoo Na ,  Seongmin Son ,  Kyuha Lee ,  Yikoan Hong

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/06 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05176 ,  H01L2224/05554 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05649 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06177 ,  H01L2224/06505 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/32145

Abstract: A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures.

公开(公告)号：US11296045B2

公开(公告)日：2022-04-05

申请号：US16831331

申请日：2020-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee Jang ,  Seokho Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Kyuha Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L27/146

Abstract: A semiconductor device is provided and includes first and second semiconductor chips bonded together. The first chip includes a first substrate, a first insulating layer disposed on the first substrate and having a top surface, a first metal pad embedded in the first insulating layer and having a top surface substantially planar with the top surface of the first insulating layer, and a first barrier disposed between the first insulating layer and the first metal pad. The second chip includes a second substrate, a second insulating layer, a second metal pad, and a second barrier with a similar configuration to the first chip. The top surfaces of the first and second insulating layers are bonded to provide a bonding interface, the first and second metal pads are connected, and a portion of the first insulating layer is in contact with a side region of the first metal pad.

公开(公告)号：US20220013502A1

公开(公告)日：2022-01-13

申请号：US17194575

申请日：2021-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuha Lee ,  Joohee Jang ,  Seokho Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Seongmin Son ,  Yikoan Hong

IPC: H01L25/065 ,  H01L23/538

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, first main connection pad structures, and first dummy connection pad structures. The first main connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip and arranged to be apart from each other by a first main pitch in a first direction parallel to a top surface of the first semiconductor chip, wherein each of the first main connection pad structures includes a first connection pad electrically connected to the first semiconductor chip, and a second connection pad electrically connected to the second semiconductor chip and contacting the first connection pad. The first dummy connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip, are arranged to be apart from the first main connection pad structures, and are arranged to be apart from each other by a first dummy pitch in the first direction, the first dummy pitch being greater than the first main pitch.

公开(公告)号：US20210066224A1

公开(公告)日：2021-03-04

申请号：US16831331

申请日：2020-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee Jang ,  Seokho Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Kyuha Lee

IPC: H01L23/00 ,  H01L27/146

Abstract: A semiconductor device is provided and includes first and second semiconductor chips bonded together. The first chip includes a first substrate, a first insulating layer disposed on the first substrate and having a top surface, a first metal pad embedded in the first insulating layer and having a top surface substantially planar with the top surface of the first insulating layer, and a first barrier disposed between the first insulating layer and the first metal pad. The second chip includes a second substrate, a second insulating layer, a second metal pad, and a second barrier with a similar configuration to the first chip. The top surfaces of the first and second insulating layers are bonded to provide a bonding interface, the first and second metal pads are connected, and a portion of the first insulating layer is in contact with a side region of the first metal pad.

公开(公告)号：US20190081148A1

公开(公告)日：2019-03-14

申请号：US15938716

申请日：2018-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun Chung ,  Jae-Jung Kim ,  Jinkyu Jang ,  Sangyong Kim ,  Hoonjoo Na ,  Dongsoo Lee ,  Sangjin Hyun

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/51 ,  H01L21/28

Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

公开(公告)号：US12142588B2

公开(公告)日：2024-11-12

申请号：US18126205

申请日：2023-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee Jang ,  Seokho Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Kyuha Lee

IPC: H01L27/146 ,  H01L23/00

Abstract: A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.