公开(公告)号：US11887841B2

公开(公告)日：2024-01-30

申请号：US17194575

申请日：2021-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuha Lee ,  Joohee Jang ,  Seokho Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Seongmin Son ,  Yikoan Hong

IPC: H01L25/065 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, first main connection pad structures, and first dummy connection pad structures. The first main connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip and arranged to be apart from each other by a first main pitch in a first direction parallel to a top surface of the first semiconductor chip, wherein each of the first main connection pad structures includes a first connection pad electrically connected to the first semiconductor chip, and a second connection pad electrically connected to the second semiconductor chip and contacting the first connection pad. The first dummy connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip, are arranged to be apart from the first main connection pad structures, and are arranged to be apart from each other by a first dummy pitch in the first direction, the first dummy pitch being greater than the first main pitch.

公开(公告)号：US12136602B2

公开(公告)日：2024-11-05

申请号：US17501133

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il Choi ,  Pil-Kyu Kang ,  Hoechul Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Seongmin Son

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L27/146

Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

公开(公告)号：US20210066250A1

公开(公告)日：2021-03-04

申请号：US16855352

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuha Lee ,  Pilkyu Kang ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Jaehyung Park ,  Joohee Jang ,  Yikoan Hong

IPC: H01L25/065 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor device according to example embodiments includes: sequentially forming first through third insulating layers on a substrate; forming an opening by etching the first through third insulating layers; forming a conductive layer configured in the opening; forming a fourth insulating layer in the opening after the forming of the conductive layer; and removing a portion of an edge region of the substrate after the forming of the fourth insulating layer.

公开(公告)号：US11824035B2

公开(公告)日：2023-11-21

申请号：US17826756

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyung Park ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Kyuha Lee ,  Joohee Jang

IPC: H01L23/00 ,  H10K19/20 ,  H10K39/32 ,  H01L27/146

CPC classification number: H01L24/32 ,  H01L24/83 ,  H10K19/20 ,  H10K39/32 ,  H01L27/14647 ,  H01L2224/32145 ,  H01L2224/32501 ,  H01L2224/83359 ,  H01L2224/83895 ,  H01L2224/83896

Abstract: A semiconductor device includes a first adsorption layer, a first bonding layer, a second bonding layer, and a second adsorption layer stacked on a first substrate, and a conductive pattern structure penetrating through the first adsorption layer, the first bonding layer, the second bonding layer and the second adsorption layer. The first and second bonding layers are in contact with each other, and each of the first and second adsorption layers includes a low-κ dielectric material.

公开(公告)号：US11658139B2

公开(公告)日：2023-05-23

申请号：US17206337

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyung Park ,  Seokho Kim ,  Hoonjoo Na ,  Seongmin Son ,  Kyuha Lee ,  Yikoan Hong

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/06 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05176 ,  H01L2224/05554 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05649 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06177 ,  H01L2224/06505 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/32145

Abstract: A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures.

公开(公告)号：US11296045B2

公开(公告)日：2022-04-05

申请号：US16831331

申请日：2020-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee Jang ,  Seokho Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Kyuha Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L27/146

Abstract: A semiconductor device is provided and includes first and second semiconductor chips bonded together. The first chip includes a first substrate, a first insulating layer disposed on the first substrate and having a top surface, a first metal pad embedded in the first insulating layer and having a top surface substantially planar with the top surface of the first insulating layer, and a first barrier disposed between the first insulating layer and the first metal pad. The second chip includes a second substrate, a second insulating layer, a second metal pad, and a second barrier with a similar configuration to the first chip. The top surfaces of the first and second insulating layers are bonded to provide a bonding interface, the first and second metal pads are connected, and a portion of the first insulating layer is in contact with a side region of the first metal pad.

公开(公告)号：US20220013502A1

公开(公告)日：2022-01-13

申请号：US17194575

申请日：2021-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuha Lee ,  Joohee Jang ,  Seokho Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Seongmin Son ,  Yikoan Hong

IPC: H01L25/065 ,  H01L23/538

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, first main connection pad structures, and first dummy connection pad structures. The first main connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip and arranged to be apart from each other by a first main pitch in a first direction parallel to a top surface of the first semiconductor chip, wherein each of the first main connection pad structures includes a first connection pad electrically connected to the first semiconductor chip, and a second connection pad electrically connected to the second semiconductor chip and contacting the first connection pad. The first dummy connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip, are arranged to be apart from the first main connection pad structures, and are arranged to be apart from each other by a first dummy pitch in the first direction, the first dummy pitch being greater than the first main pitch.

公开(公告)号：US20210066224A1

公开(公告)日：2021-03-04

申请号：US16831331

申请日：2020-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee Jang ,  Seokho Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Kyuha Lee

IPC: H01L23/00 ,  H01L27/146

Abstract: A semiconductor device is provided and includes first and second semiconductor chips bonded together. The first chip includes a first substrate, a first insulating layer disposed on the first substrate and having a top surface, a first metal pad embedded in the first insulating layer and having a top surface substantially planar with the top surface of the first insulating layer, and a first barrier disposed between the first insulating layer and the first metal pad. The second chip includes a second substrate, a second insulating layer, a second metal pad, and a second barrier with a similar configuration to the first chip. The top surfaces of the first and second insulating layers are bonded to provide a bonding interface, the first and second metal pads are connected, and a portion of the first insulating layer is in contact with a side region of the first metal pad.

公开(公告)号：US20240049445A1

公开(公告)日：2024-02-08

申请号：US18355429

申请日：2023-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoju Song ,  Eunjung Kim ,  Kihyung Nam ,  Jaehyung Park ,  Yunjae Lee

IPC: H10B12/00

CPC classification number: H10B12/09 ,  H10B12/315 ,  H10B12/50

Abstract: A method of manufacturing a semiconductor device may include forming word lines in word line trenches on a substrate, removing a portion of the substrate located between a pair of the word lines to form a direct contact hole, forming on an inner wall of the direct contact hole a sacrificial liner structure that includes a first liner, a sacrificial layer, and a second liner, forming a preliminary direct contact in the direct contact hole, removing the sacrificial layer, while leaving the first and second liners, to form an air space between the first and second liners, forming a bit line stack that covers an upper surface the air space on the preliminary direct contact, patterning the bit line stack to form bit lines, and removing side portions of the second liner and the preliminary direct contact in the direct contact hole to form a direct contact.

公开(公告)号：US11616036B2

公开(公告)日：2023-03-28

申请号：US17694035

申请日：2022-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee Jang ,  Seokho Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Kyuha Lee

IPC: H01L27/146 ,  H01L23/00

Abstract: A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.