公开(公告)号：US20140154863A1

公开(公告)日：2014-06-05

申请号：US14016254

申请日：2013-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Woo Seo

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10852 ,  H01L27/10876 ,  H01L28/86 ,  H01L28/90

Abstract: A method of forming semiconductor device includes forming a landing pad, forming a stopping insulating layer on the landing pad, forming a lower molding layer including a first material on the stopping insulating layer, forming an upper molding layer including a second material different from the first material on the lower molding layer, forming a hole vertically passing through the upper molding layer and the lower molding layer and exposing the landing pad, forming a first electrode in the hole, removing the upper molding layer to expose a part of a surface of the first electrode, removing the lower molding layer to expose another part of the surface of the first electrode, forming a capacitor dielectric layer on the exposed parts of the surface of the first electrode, and forming a second electrode on the dielectric layer.

Abstract translation: 一种形成半导体器件的方法包括：形成一个着陆焊盘，在着陆焊盘上形成一个止动绝缘层，在该止动绝缘层上形成一个包含第一材料的下模塑层，形成一个上模制层， 在下成型层上形成材料，形成垂直穿过上模制层和下成型层的孔，并露出着陆垫，在孔中形成第一电极，去除上模制层以暴露出一部分表面 第一电极，去除下模制层以暴露第一电极的表面的另一部分，在第一电极的表面的暴露部分上形成电容器介电层，并在电介质层上形成第二电极。

公开(公告)号：US09324609B2

公开(公告)日：2016-04-26

申请号：US14673169

申请日：2015-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Won Kim ,  Jung-Woo Seo

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/56 ,  H01L21/02 ,  H01L21/033 ,  H01L49/02 ,  H01L21/311

CPC classification number: H01L21/76877 ,  H01L21/02164 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/3135 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L28/40 ,  H01L28/91

Abstract: Methods of forming a hard mask capable of implementing an electrode having a high aspect ratio are provided. A molding layer may be formed on a substrate. A sacrificial layer may be formed on the molding layer. First mask patterns may be formed in parallel in the sacrificial layer. After the first mask patterns are formed, second mask patterns, which cross the first mask patterns and are in parallel, may be formed in the sacrificial layer. The first mask patterns and the second mask patterns may have materials more opaque than the sacrificial layer. Upper surfaces of the sacrificial layer, the first mask patterns and the second mask patterns may be exposed at the same horizontal level. The sacrificial layer may be removed. Openings, which pass through the molding layer, may be formed using the first mask patterns and the second mask patterns as etch masks. Electrodes may be formed in the openings.

Abstract translation: 提供了形成能够实现具有高纵横比的电极的硬掩模的方法。 可以在基板上形成成型层。 可以在模制层上形成牺牲层。 可以在牺牲层中平行地形成第一掩模图案。 在形成第一掩模图案之后，可以在牺牲层中形成穿过第一掩模图案并且平行的第二掩模图案。 第一掩模图案和第二掩模图案可以具有比牺牲层更不透明的材料。 牺牲层的上表面，第一掩模图案和第二掩模图案可以以相同的水平面曝光。 牺牲层可以被去除。 通过成型层的开口可以使用第一掩模图案和第二掩模图案作为蚀刻掩模来形成。 电极可以形成在开口中。

公开(公告)号：US20150364366A1

公开(公告)日：2015-12-17

申请号：US14673169

申请日：2015-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Won KIM ,  Jung-Woo Seo

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L49/02 ,  H01L21/311 ,  H01L21/56 ,  H01L21/033

CPC classification number: H01L21/76877 ,  H01L21/02164 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/3135 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L28/40 ,  H01L28/91

Abstract: Methods of forming a hard mask capable of implementing an electrode having a high aspect ratio are provided. A molding layer may be formed on a substrate. A sacrificial layer may be formed on the molding layer. First mask patterns may be formed in parallel in the sacrificial layer. After the first mask patterns are formed, second mask patterns, which cross the first mask patterns and are in parallel, may be formed in the sacrificial layer. The first mask patterns and the second mask patterns may have materials more opaque than the sacrificial layer. Upper surfaces of the sacrificial layer, the first mask patterns and the second mask patterns may be exposed at the same horizontal level. The sacrificial layer may be removed. Openings, which pass through the molding layer, may be formed using the first mask patterns and the second mask patterns as etch masks. Electrodes may be formed in the openings.

Abstract translation: 提供了形成能够实现具有高纵横比的电极的硬掩模的方法。 可以在基板上形成成型层。 可以在模制层上形成牺牲层。 可以在牺牲层中平行地形成第一掩模图案。 在形成第一掩模图案之后，可以在牺牲层中形成穿过第一掩模图案并且平行的第二掩模图案。 第一掩模图案和第二掩模图案可以具有比牺牲层更不透明的材料。 牺牲层的上表面，第一掩模图案和第二掩模图案可以以相同的水平面曝光。 牺牲层可以被去除。 通过成型层的开口可以使用第一掩模图案和第二掩模图案作为蚀刻掩模来形成。 电极可以形成在开口中。