公开(公告)号：US20160225845A1

公开(公告)日：2016-08-04

申请号：US15087349

申请日：2016-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Seung Cho ,  Sung-Eui Kim ,  Ji-Young Kim ,  Hoon Jeong ,  Chan-Won Kim ,  Jong-Bom Seo ,  Seung-Jun Lee ,  Jun-Soo Lee

IPC: H01L49/02

CPC classification number: H01L28/88 ,  H01L21/764 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/90

Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.

Abstract translation: 半导体器件包括第一电容器结构，第二电容器结构和绝缘图案。 第一电容器结构包括顺序堆叠在基板上的第一下电极，第一电介质层和第一上电极。 第二电容器结构包括第二下电极，第二电介质层和顺序堆叠在基板上并与第一电容器结构相邻的第二上电极。 绝缘图案部分地填充第一和第二电容器结构之间的空间，并且在绝缘图案上的第一和第二电容器结构之间形成气隙。

公开(公告)号：US09793133B2

公开(公告)日：2017-10-17

申请号：US14509828

申请日：2014-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Won Kim ,  Jung-Woo Seo ,  Kee-Hong Lee ,  Kyoung-Ryul Yoon ,  Seong-Kyu Yun

IPC: H01L21/311 ,  H01L27/108 ,  H01L49/02

CPC classification number: H01L21/311 ,  H01L21/31116 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L28/90

Abstract: Methods of forming a semiconductor device can be provided by forming a first molding layer on a substrate and forming a first hole through the first molding layer. A second molding layer can be formed on the first molding layer so that the first hole is retained in the first molding layer and a second hole can be formed through the second molding layer to connect with the first hole. A capacitor electrode can be formed in the first and second holes.

公开(公告)号：US09431476B2

公开(公告)日：2016-08-30

申请号：US15087349

申请日：2016-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Seung Cho ,  Sung-Eui Kim ,  Ji-Young Kim ,  Hoon Jeong ,  Chan-Won Kim ,  Jong-Bom Seo ,  Seung-Jun Lee ,  Jun-Soo Lee

IPC: H01L21/00 ,  H01L49/02 ,  H01L27/108 ,  H01L21/764

CPC classification number: H01L28/88 ,  H01L21/764 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/90

Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.

Abstract translation: 半导体器件包括第一电容器结构，第二电容器结构和绝缘图案。 第一电容器结构包括顺序堆叠在基板上的第一下电极，第一电介质层和第一上电极。 第二电容器结构包括第二下电极，第二电介质层和顺序堆叠在基板上并与第一电容器结构相邻的第二上电极。 绝缘图案部分地填充第一和第二电容器结构之间的空间，并且在绝缘图案上的第一和第二电容器结构之间形成气隙。

公开(公告)号：US09324609B2

公开(公告)日：2016-04-26

申请号：US14673169

申请日：2015-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Won Kim ,  Jung-Woo Seo

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/56 ,  H01L21/02 ,  H01L21/033 ,  H01L49/02 ,  H01L21/311

CPC classification number: H01L21/76877 ,  H01L21/02164 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/3135 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L28/40 ,  H01L28/91

Abstract: Methods of forming a hard mask capable of implementing an electrode having a high aspect ratio are provided. A molding layer may be formed on a substrate. A sacrificial layer may be formed on the molding layer. First mask patterns may be formed in parallel in the sacrificial layer. After the first mask patterns are formed, second mask patterns, which cross the first mask patterns and are in parallel, may be formed in the sacrificial layer. The first mask patterns and the second mask patterns may have materials more opaque than the sacrificial layer. Upper surfaces of the sacrificial layer, the first mask patterns and the second mask patterns may be exposed at the same horizontal level. The sacrificial layer may be removed. Openings, which pass through the molding layer, may be formed using the first mask patterns and the second mask patterns as etch masks. Electrodes may be formed in the openings.

Abstract translation: 提供了形成能够实现具有高纵横比的电极的硬掩模的方法。 可以在基板上形成成型层。 可以在模制层上形成牺牲层。 可以在牺牲层中平行地形成第一掩模图案。 在形成第一掩模图案之后，可以在牺牲层中形成穿过第一掩模图案并且平行的第二掩模图案。 第一掩模图案和第二掩模图案可以具有比牺牲层更不透明的材料。 牺牲层的上表面，第一掩模图案和第二掩模图案可以以相同的水平面曝光。 牺牲层可以被去除。 通过成型层的开口可以使用第一掩模图案和第二掩模图案作为蚀刻掩模来形成。 电极可以形成在开口中。

公开(公告)号：US09123657B2

公开(公告)日：2015-09-01

申请号：US14326960

申请日：2014-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjoon Park ,  Junho Yoon ,  Je-Woo Han ,  Chan-Won Kim

IPC: H01L21/76 ,  H01L21/308 ,  H01L49/02

CPC classification number: H01L21/3086 ,  H01L21/3085 ,  H01L21/31144 ,  H01L23/544 ,  H01L28/40 ,  H01L28/91 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an interlayer insulating layer on a structure with a cell region and a peripheral circuit region, forming a first mask layer on the interlayer insulating layer, forming trenches in the first mask layer exposing the interlayer insulating layer by patterning the first mask layer on the peripheral circuit region, and forming key mask patterns in the trenches. An etch selectivity of the first mask patterns with respect to the interlayer insulating layer may be greater than that of the key mask patterns with respect to the interlayer insulating layer.

Abstract translation: 提供一种制造半导体器件的方法。 该方法可以包括在具有单元区域和外围电路区域的结构上形成层间绝缘层，在层间绝缘层上形成第一掩模层，在第一掩模层中形成沟槽，通过图案化第一掩模 并且在沟槽中形成键掩模图案。 第一掩模图案相对于层间绝缘层的蚀刻选择性可以大于键层掩模图案相对于层间绝缘层的蚀刻选择性。