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    Semiconductor devices
    1.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US10700074B2

    公开(公告)日：2020-06-30

    申请号：US16782213

    申请日：2020-02-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun-Kyum Kim ,  Jung-Woo Seo ,  Sung-Un Kwon

    IPC: H01L23/52 ,  H01L27/108 ,  H01L21/768

    Abstract: A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.

    Method of forming semiconductor device
    3.
    发明授权
    Method of forming semiconductor device 有权
    半导体器件形成方法

    公开(公告)号：US09177960B2

    公开(公告)日：2015-11-03

    申请号：US14016254

    申请日：2013-09-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung-Woo Seo

    IPC: H01L29/66 ,  H01L21/336 ,  H01L27/108 ,  H01L49/02

    CPC classification number: H01L27/10814 ,  H01L27/10852 ,  H01L27/10876 ,  H01L28/86 ,  H01L28/90

    Abstract: A method of forming semiconductor device includes forming a landing pad, forming a stopping insulating layer on the landing pad, forming a lower molding layer including a first material on the stopping insulating layer, forming an upper molding layer including a second material different from the first material on the lower molding layer, forming a hole vertically passing through the upper molding layer and the lower molding layer and exposing the landing pad, forming a first electrode in the hole, removing the upper molding layer to expose a part of a surface of the first electrode, removing the lower molding layer to expose another part of the surface of the first electrode, forming a capacitor dielectric layer on the exposed parts of the surface of the first electrode, and forming a second electrode on the dielectric layer.

    Abstract translation: 一种形成半导体器件的方法包括：形成一个着陆焊盘，在着陆焊盘上形成一个止动绝缘层，在该止动绝缘层上形成一个包含第一材料的下模塑层，形成一个上模制层， 在下成型层上形成材料，形成垂直穿过上模制层和下成型层的孔，并露出着陆垫，在孔中形成第一电极，去除上模制层以暴露出一部分表面 第一电极，去除下模制层以暴露第一电极的表面的另一部分，在第一电极的表面的暴露部分上形成电容器介电层，并在电介质层上形成第二电极。

    Methods of forming hole patterns of semiconductor devices
    4.
    发明授权
    Methods of forming hole patterns of semiconductor devices 有权
    形成半导体器件孔图案的方法

    公开(公告)号：US09159560B2

    公开(公告)日：2015-10-13

    申请号：US14043361

    申请日：2013-10-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Woo Seo

    IPC: H01L21/31 ,  H01L21/033 ,  H01L21/3213

    CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/32139

    Abstract: A double patterning method of forming a plurality of hole patterns having a small pitch using etch selectivities includes forming a patterning mask pattern defining a preliminary hole exposing an upper surface of a buffer mask layer, an inner spacer exposing the upper surface of the buffer mask layer on an inner wall of the preliminary hole, a buffer mask pattern having a first hole, and a core insulating pattern filling the preliminary hole and the first hole, an outer spacer to expose a first portion of the patterning mask pattern on the exposed portion of the outer side of the inner spacer, and an empty space exposing a first portion of the buffer mask pattern. A second portion of the patterning mask pattern and a second portion of the buffer mask pattern are exposed. A second hole is formed by removing the second portion of the buffer mask pattern.

    Abstract translation: 使用蚀刻选择性形成具有小间距的多个孔图案的双重图案化方法包括形成限定暴露缓冲掩模层的上表面的预备孔的图案化掩模图案，暴露缓冲掩模层的上表面的内部间隔 在预备孔的内壁上，具有第一孔的缓冲掩模图案和填充预备孔和第一孔的芯绝缘图案，将外部间隔物露出在图案形成掩模图案的暴露部分的第一部分上 内部间隔物的外侧，以及露出缓冲掩模图案的第一部分的空白空间。 图案化掩模图案的第二部分和缓冲掩模图案的第二部分被暴露。 通过去除缓冲掩模图案的第二部分来形成第二孔。

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