公开(公告)号：US20230040733A1

公开(公告)日：2023-02-09

申请号：US17846606

申请日：2022-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisu YU ,  Woojin RIM ,  Jungho DO ,  Jaewoo SEO ,  Hyeongyu YOU ,  Minjae JEONG

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238

Abstract: Provided is an integrated circuit including standard cells arranged over a plurality of rows. The standard cells may include: a plurality of functional cells each implemented as a logic circuit; and a plurality of filler cells including at least one first filler cell and at least one second filler cell that each include at least one pattern from among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern, and wherein the at least one first filler cell and the at least one second filler cell have a same size as each other, and a density of one of the at least one pattern of the at least one first filler cell is different from a density of one of the at least one pattern of the at least one second filler cell.

公开(公告)号：US20220122970A1

公开(公告)日：2022-04-21

申请号：US17323707

申请日：2021-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungho DO ,  Sanghoon BAEK

IPC: H01L27/088 ,  H01L29/66 ,  H01L27/06 ,  H01L23/50 ,  H01L23/522 ,  H01L29/78

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first dummy region and a second dummy region spaced apart from the first dummy region; a device isolation layer filling a trench between the first dummy region and the second dummy region; a first dummy electrode provided on the first dummy region; a second dummy electrode provided on the second dummy region; a power line extending from the first dummy region to the second dummy region, the power line including an expanded portion provided on the device isolation layer, a width of the expanded portion being larger than a line width of a remaining portion of the power line; a power delivery network provided on a bottom surface of the substrate; and a through via extending through the substrate and the device isolation layer, and electrically connecting the power delivery network to the expanded portion. The through via and the expanded portion vertically overlap.

公开(公告)号：US20240413151A1

公开(公告)日：2024-12-12

申请号：US18808934

申请日：2024-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungho DO ,  Sanghoon Baek

IPC: H01L27/088 ,  H01L23/50 ,  H01L23/522 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first dummy region and a second dummy region spaced apart from the first dummy region; a device isolation layer filling a trench between the first dummy region and the second dummy region; a first dummy electrode provided on the first dummy region; a second dummy electrode provided on the second dummy region; a power line extending from the first dummy region to the second dummy region, the power line including an expanded portion provided on the device isolation layer, a width of the expanded portion being larger than a line width of a remaining portion of the power line; a power delivery network provided on a bottom surface of the substrate; and a through via extending through the substrate and the device isolation layer, and electrically connecting the power delivery network to the expanded portion. The through via and the expanded portion vertically overlap.

公开(公告)号：US20240332305A1

公开(公告)日：2024-10-03

申请号：US18743961

申请日：2024-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon BAEK ,  Jungho DO ,  Jaewoo SEO ,  Jisu YU

IPC: H01L27/118 ,  H01L23/48 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L23/481 ,  H01L27/0207 ,  H01L2027/11829 ,  H01L2027/11864 ,  H01L2027/11881

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

公开(公告)号：US20230335559A1

公开(公告)日：2023-10-19

申请号：US18336754

申请日：2023-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon BAEK ,  Jungho DO ,  Jaewoo SEO ,  Jisu YU

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/48

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L23/481 ,  H01L2027/11864 ,  H01L2027/11881 ,  H01L2027/11829

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

公开(公告)号：US20220300693A1

公开(公告)日：2022-09-22

申请号：US17669631

申请日：2022-02-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungho DO ,  Jaewoo SEO ,  Sanghoon BAEK ,  Jisu YU ,  Hyeongyu YOU ,  Minjae JEONG

IPC: G06F30/394 ,  G06F30/392

Abstract: An integrated circuit includes a first cell including a first lower pattern extending in a first direction along a first track in a first wiring layer; and a second cell including a second lower pattern that extends in the first direction along the first track in the first wiring layer, and is a minimum space of the first wiring layer or farther apart from the first lower pattern, wherein the first lower pattern corresponds to a pin of the first cell, and the second lower pattern is farther apart from a boundary between the first cell and the second cell than the first lower pattern is.

公开(公告)号：US20190268000A1

公开(公告)日：2019-08-29

申请号：US16159196

申请日：2018-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Jungho DO ,  Seungyoung LEE ,  Jonghoon JUNG

IPC: H03K19/177 ,  H01L27/02 ,  H01L27/088 ,  H01L23/528 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active patterns that extend in a second direction intersecting the first direction and that are spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active patterns, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active pattern of the first logic cell from the first active pattern of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.