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    STACKED INTEGRATED CIRCUIT DEVICES
    1.
    发明公开
    STACKED INTEGRATED CIRCUIT DEVICES 审中-公开

    公开(公告)号：US20240274510A1

    公开(公告)日：2024-08-15

    申请号：US18646015

    申请日：2024-04-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Ho DO ,  Seungyoung LEE

    IPC: H01L23/48 ,  H01L27/02 ,  H01L27/088

    CPC classification number: H01L23/481 ,  H01L27/0207 ,  H01L27/088

    Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.

    CROSS-COUPLED GATE DESIGN FOR STACKED DEVICE WITH SEPARATED TOP-DOWN GATE
    2.
    发明申请
    CROSS-COUPLED GATE DESIGN FOR STACKED DEVICE WITH SEPARATED TOP-DOWN GATE 有权

    公开(公告)号：US20220246610A1

    公开(公告)日：2022-08-04

    申请号：US17221355

    申请日：2021-04-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunghyun SONG ,  Seungyoung LEE ,  Saehan PARK

    IPC: H01L27/092 ,  H01L29/423 ,  H01L21/8238

    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a cross-coupled gate circuit in a three-dimensional (3D) stack including a plurality of transistors, a first gate line of a first transistor among the plurality of transistors connected to a fourth gate line of a fourth transistor among the plurality of transistors, a second gate line of a second transistor among the plurality of transistors connected to a third gate line of a third transistor among the plurality of transistors, a first conductor connecting the first gate line and the fourth gate line, a second conductor connecting the second gate line and the third gate line. The first gate line and the second gate line are arranged above the third gate line and the fourth gate line, respectively.

    STACKED SEMICONDUCTOR DEVICE ARCHITECTURE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    STACKED SEMICONDUCTOR DEVICE ARCHITECTURE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220230961A1

    公开(公告)日：2022-07-21

    申请号：US17220643

    申请日：2021-04-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Saehan PARK ,  Seungyoung LEE

    IPC: H01L23/528

    Abstract: Provided is a semiconductor architecture having a metal-oxide-semiconductor field-effect transistor (MOSFET) cell, the semiconductor architecture including a first semiconductor device included in the MOSFET cell, a second semiconductor device included in the MOSFET cell, the second semiconductor device being provided above the first semiconductor device, a first power rail configured to supply power to the first semiconductor device, the first power rail being provided at a vertical level different from the first semiconductor device and the second semiconductor device, and a second power rail configured to supply power to the second semiconductor device, the second power rail being provided at a vertical level between the first semiconductor device and the second semiconductor device.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210050854A1

    公开(公告)日：2021-02-18

    申请号：US17088819

    申请日：2020-11-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejoong SONG ,  Jungho DO ,  Seungyoung LEE ,  Jonghoon JUNG

    IPC: H03K19/17724 ,  H01L27/02 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L27/088

    Abstract: A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200076436A1

    公开(公告)日：2020-03-05

    申请号：US16677165

    申请日：2019-11-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taejoong SONG ,  Jungho DO ,  Seungyoung LEE ,  Jonghoon JUNG

    IPC: H03K19/177 ,  H01L27/02 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L27/088

    Abstract: A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

    SELECTIVE DOUBLE DIFFUSION BREAK STRUCTURES FOR MULTI-STACK SEMICONDUCTOR DEVICE
    6.
    发明申请
    SELECTIVE DOUBLE DIFFUSION BREAK STRUCTURES FOR MULTI-STACK SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250031360A1

    公开(公告)日：2025-01-23

    申请号：US18905663

    申请日：2024-10-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byounghak HONG ,  Seunghyun SONG ,  Saehan PARK ,  Seungyoung LEE ,  Inchan HWANG

    IPC: H10B10/00 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

    Abstract: A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190268000A1

    公开(公告)日：2019-08-29

    申请号：US16159196

    申请日：2018-10-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taejoong SONG ,  Jungho DO ,  Seungyoung LEE ,  Jonghoon JUNG

    IPC: H03K19/177 ,  H01L27/02 ,  H01L27/088 ,  H01L23/528 ,  H01L29/423 ,  H01L29/06

    Abstract: A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active patterns that extend in a second direction intersecting the first direction and that are spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active patterns, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active pattern of the first logic cell from the first active pattern of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

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