公开(公告)号：US12217786B2

公开(公告)日：2025-02-04

申请号：US18613361

申请日：2024-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hijung Kim ,  Hoyoun Kim ,  Jungmin You ,  Seongjin Cho

IPC: G11C11/00 ,  G06F7/544 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4094

Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.

公开(公告)号：US20240304234A1

公开(公告)日：2024-09-12

申请号：US18669714

申请日：2024-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin You ,  Seongjin Cho

IPC: G11C11/408 ,  G11C11/406

CPC classification number: G11C11/4087 ,  G11C11/406

Abstract: A method of controlling a row hammer swaps a first address entry with a second address entry having the smallest second access number and randomly swaps the first address entry with a third address entry having a third access number which is not the greatest value, in an address table representing a correlation between an address entry accessed during a row hammer monitoring time frame and an access number, thereby preventing a hacker-pattern row hammer aggression from being easily performed.

公开(公告)号：US12027199B2

公开(公告)日：2024-07-02

申请号：US17707034

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin You ,  Seongjin Cho

IPC: G11C11/408 ,  G11C11/406

CPC classification number: G11C11/4087 ,  G11C11/406

Abstract: A method of controlling a row hammer swaps a first address entry with a second address entry having the smallest second access number and randomly swaps the first address entry with a third address entry having a third access number which is not the greatest value, in an address table representing a correlation between an address entry accessed during a row hammer monitoring time frame and an access number, thereby preventing a hacker-pattern row hammer aggression from being easily performed.

公开(公告)号：US11961550B2

公开(公告)日：2024-04-16

申请号：US17735542

申请日：2022-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hijung Kim ,  Hoyoun Kim ,  Jungmin You ,  Seongjin Cho

IPC: G11C11/00 ,  G06F7/544 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/40622 ,  G06F7/5443 ,  G11C11/40611 ,  G11C11/4085 ,  G11C11/4094

Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.

公开(公告)号：US20230044186A1

公开(公告)日：2023-02-09

申请号：US17741604

申请日：2022-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin You ,  Wonhyung Song ,  Hoyoun Kim

IPC: G11C11/406 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.