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    MEMORY CONTROLLERS, MEMORY SYSTEMS INCLUDING THE SAME AND MEMORY MODULES
    1.
    发明申请
    MEMORY CONTROLLERS, MEMORY SYSTEMS INCLUDING THE SAME AND MEMORY MODULES 有权

    公开(公告)号：US20210133028A1

    公开(公告)日：2021-05-06

    申请号：US16878793

    申请日：2020-05-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunjoong Kim ,  Taekwoon Kim ,  Younghoe Kim ,  Wonhyung Song ,  Jangseok Choi ,  Joonseok Choi

    IPC: G06F11/10

    Abstract: A memory controller configured to control a memory module including a plurality of memory devices which constitute a first channel and a second channel includes an error correction code (ECC) engine, and a control circuit configured to control the ECC engine. The ECC engine is configured to generate a codeword including a plurality of symbols by adaptively constructing, based on device information including mapping information, each of the plurality of symbols from a predetermined number of data bits received via a plurality of input/output pads of each of the plurality of memory devices, and transmit the codeword to the memory module. The mapping information indicates whether each of the plurality of input/output pads is mapped to the same symbol among the plurality of symbols or different symbols among the plurality of symbols. Each of the plurality of symbols corresponds to a unit of error correction of the ECC engine.

    METHOD OF CONTROLLING ROW HAMMER AND A MEMORY DEVICE
    4.
    发明申请
    METHOD OF CONTROLLING ROW HAMMER AND A MEMORY DEVICE 有权

    公开(公告)号：US20230044186A1

    公开(公告)日：2023-02-09

    申请号：US17741604

    申请日：2022-05-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungmin You ,  Wonhyung Song ,  Hoyoun Kim

    IPC: G11C11/406 ,  G11C11/4093 ,  G11C11/4096

    Abstract: A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.

    Memory module with reduced ECC overhead and memory system
    5.
    发明授权
    Memory module with reduced ECC overhead and memory system 有权

    公开(公告)号：US11222709B2

    公开(公告)日：2022-01-11

    申请号：US16916463

    申请日：2020-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taekwoon Kim ,  Wonhyung Song ,  Jangseok Choi

    IPC: G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/32 ,  G11C29/12

    Abstract: A memory system includes a memory module and a memory controller. The memory module includes data chips that store data and are assigned to a first sub-channel that generates a first code word or a second sub-channel that generates a second code word, where the first code word and the second code are used to fill a single cache line. The memory controller, upon detection of a hard-fail data chip among the data chips, copies data from the hard-fail data chip to the ECC chip, releases mapping between the hard-fail data chip and corresponding I/O, and defines new mapping between the ECC chip and the corresponding I/O pins.

    Memory controllers, memory systems including the same and memory modules
    6.
    发明授权
    Memory controllers, memory systems including the same and memory modules 有权

    公开(公告)号：US11068347B2

    公开(公告)日：2021-07-20

    申请号：US16878793

    申请日：2020-05-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunjoong Kim ,  Taekwoon Kim ,  Younghoe Kim ,  Wonhyung Song ,  Jangseok Choi ,  Joonseok Choi

    IPC: G06F11/00 ,  G06F11/10

    Abstract: A memory controller configured to control a memory module including a plurality of memory devices which constitute a first channel and a second channel includes an error correction code (ECC) engine, and a control circuit configured to control the ECC engine. The ECC engine is configured to generate a codeword including a plurality of symbols by adaptively constructing, based on device information including mapping information, each of the plurality of symbols from a predetermined number of data bits received via a plurality of input/output pads of each of the plurality of memory devices, and transmit the codeword to the memory module. The mapping information indicates whether each of the plurality of input/output pads is mapped to the same symbol among the plurality of symbols or different symbols among the plurality of symbols. Each of the plurality of symbols corresponds to a unit of error correction of the ECC engine.

    Method of controlling row hammer and a memory device
    7.
    发明授权
    Method of controlling row hammer and a memory device 有权

    公开(公告)号：US11967352B2

    公开(公告)日：2024-04-23

    申请号：US17741604

    申请日：2022-05-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungmin You ,  Wonhyung Song ,  Hoyoun Kim

    IPC: G11C11/406 ,  G11C11/4093 ,  G11C11/4096

    CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/4093 ,  G11C11/4096

    Abstract: A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.

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