公开(公告)号：US11815997B2

公开(公告)日：2023-11-14

申请号：US17814964

申请日：2022-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhun Lim ,  Kijun Lee ,  Myungkyu Lee ,  Eunchul Kwon ,  Hoyoun Kim ,  Jongmin Lee

IPC: H03M13/00 ,  G06F11/10 ,  G06F11/07 ,  G06F17/16 ,  H03M13/15

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  G06F17/16 ,  H03M13/1575

Abstract: A memory controller includes an error correction code (ECC) engine and an error managing circuit. The ECC engine is configured to, during a read operation, perform an ECC decoding on a read codeword set to generate a first and second syndrome associated with a correctable error in a user data set included in the read codeword set, correct the correctable error based on the first syndrome and the second syndrome, and provide the second syndrome to the error managing circuit. The error managing circuit is configured to accumulate second syndromes associated with a plurality of correctable errors and obtained through a plurality of read operations as a plurality of second syndromes, store the plurality of second syndromes, compare the plurality of second syndromes with an error pattern set, and predict an occurrence of an uncorrectable error associated with the correctable error in a memory region based on the comparison.

公开(公告)号：US11437115B2

公开(公告)日：2022-09-06

申请号：US17326416

申请日：2021-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Hoyoun Kim ,  Suhun Lim ,  Sunghye Cho

IPC: G11C29/00 ,  G11C29/42 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, row fault detector circuitry and control logic circuitry. The memory cell array includes a plurality of memory cell rows. The control logic circuitry controls the ECC engine circuitry to perform a plurality of error detection operations on each of the memory cell rows. The control logic circuitry controls the row fault detector circuitry to store an error parameter associated with each of a plurality of codewords in each of which at least one error is detected by accumulating the error parameter for each of a plurality of defective memory cell rows. The row fault detector circuitry determines whether a row fault occurs in each of the plurality of defective memory cell rows based on a number of changes of the error parameter.

公开(公告)号：US20220100395A1

公开(公告)日：2022-03-31

申请号：US17226606

申请日：2021-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoyoun Kim ,  Kijun Lee ,  Myungkyu Lee

IPC: G06F3/06

Abstract: A memory system is provided. The memory system includes at least one memory device, and a controller configured to control the at least one memory device, wherein the controller includes: an error correction circuit configured to correct an error in data read from the at least one memory device, a codeword error counter configured to obtain a syndrome of a current codeword error based on a codeword error occurring in the error correction circuit, and to obtain a weighted codeword error count value by comparing the obtained syndrome with a previous syndrome, and an alert device configured to generate a warning signal for preventing an uncorrectable error of the at least one memory device according to the weighted codeword error count value.

公开(公告)号：US20250077349A1

公开(公告)日：2025-03-06

申请号：US18430287

申请日：2024-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoyoun Kim

IPC: G06F11/10

Abstract: A memory device includes a first memory device configured to store a first error correction code of a first size during a first write operation, a second memory device configured to store a second error correction code of a second size, larger than the first size, during a second write operation, and a control logic circuit configured to control the first memory device and the second memory device. The control logic circuit includes an error correction circuit configured to generate one of the first error correction code and the second error correction code for write data according to puncturing option information.

公开(公告)号：US20240145025A1

公开(公告)日：2024-05-02

申请号：US18380185

申请日：2023-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoyoun Kim

IPC: G11C29/52 ,  G11C7/10

CPC classification number: G11C29/52 ,  G11C7/1039 ,  G11C7/1063

Abstract: A memory controller includes an error correction code (ECC) circuit configured to receive a data burst and generate first ECC data or second ECC data, and a processor configured to control operations of the ECC circuit. The ECC circuit includes an ECC select circuit configured to select and output one of first ECC conversion data and second ECC conversion data, based on an ECC select signal from outside the memory controller, and an ECC conversion circuit configured to generate the first ECC data by encoding the data burst, based on the first ECC conversion data, or generate the second ECC data by encoding the data burst, based on the second ECC conversion data. The second ECC conversion data is set to be capable of correcting an error generated in one or more preset protected bits among bits included in each of pieces of partial data included in the data burst.

公开(公告)号：US11967352B2

公开(公告)日：2024-04-23

申请号：US17741604

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin You ,  Wonhyung Song ,  Hoyoun Kim

IPC: G11C11/406 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.

公开(公告)号：US11942137B2

公开(公告)日：2024-03-26

申请号：US17829669

申请日：2022-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoyoun Kim

IPC: G11C11/40 ,  G06F3/06 ,  G06N7/01 ,  G11C11/406

CPC classification number: G11C11/406 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G06N7/01

Abstract: A memory controller, to control a semiconductor memory device, includes an access pattern profiler, a row hammer prediction neural network, and a memory interface. The access pattern profiler generates an access pattern profile based on a row access pattern on a portion of memory cell rows of the semiconductor memory device during a reference time interval posterior to a refresh interval during which the memory cell rows are refreshed. The row hammer prediction neural network predicts a probability of occurrence based on the access pattern profile. In response to the probability being equal to or greater than a reference value, the row hammer prediction neural network generates a hammer address, an alert signal indicating that the row hammer occurs, and an outcast row list. The memory interface transmits the hammer address, the outcast row list, and the alert signal to the semiconductor memory device.

公开(公告)号：US12165689B2

公开(公告)日：2024-12-10

申请号：US17817348

申请日：2022-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoyoun Kim

IPC: G11C16/04 ,  G11C11/406 ,  G11C11/408

Abstract: A refresh control circuit includes: a counting bloom filter that includes N hash control logics, each of which performs a hash operation on input data and outputs an M-bit sequence and M counters, each of which corresponds to a bit of the M-bit sequence, and updates count values of corresponding counters indicated by values of the M-bit sequences obtained from the N hash logics by using an address of a row of the memory cells as the input data; a candidate row determiner that determines rows of the memory cells accessed in a predetermined period in which the count values of the corresponding counters are greater than a threshold value as candidate rows for a target refresh operation; and a target refresh controller that outputs target refresh signals for rows of the candidate rows adjacent to one or more target rows determined by the candidate row determiner.

公开(公告)号：US20230147227A1

公开(公告)日：2023-05-11

申请号：US17814964

申请日：2022-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhun Lim ,  Kijun Lee ,  Myungkyu Lee ,  Eunchul Kwon ,  Hoyoun Kim ,  Jongmin Lee

IPC: G06F11/10 ,  G06F11/07 ,  H03M13/15 ,  G06F17/16

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/076 ,  H03M13/1575 ,  G06F17/16

Abstract: A memory controller includes an error correction code (ECC) engine and an error managing circuit. The ECC engine is configured to, during a read operation, perform an ECC decoding on a read codeword set to generate a first and second syndrome associated with a correctable error in a user data set included in the read codeword set, correct the correctable error based on the first syndrome and the second syndrome, and provide the second syndrome to the error managing circuit. The error managing circuit is configured to accumulate second syndromes associated with a plurality of correctable errors and obtained through a plurality of read operations as a plurality of second syndromes, store the plurality of second syndromes, compare the plurality of second syndromes with an error pattern set, and predict an occurrence of an uncorrectable error associated with the correctable error in a memory region based on the comparison.

公开(公告)号：US11614869B2

公开(公告)日：2023-03-28

申请号：US17226606

申请日：2021-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoyoun Kim ,  Kijun Lee ,  Myungkyu Lee

IPC: G06F3/06

Abstract: A memory system is provided. The memory system includes at least one memory device, and a controller configured to control the at least one memory device, wherein the controller includes: an error correction circuit configured to correct an error in data read from the at least one memory device, a codeword error counter configured to obtain a syndrome of a current codeword error based on a codeword error occurring in the error correction circuit, and to obtain a weighted codeword error count value by comparing the obtained syndrome with a previous syndrome, and an alert device configured to generate a warning signal for preventing an uncorrectable error of the at least one memory device according to the weighted codeword error count value.