公开(公告)号：US11901025B2

公开(公告)日：2024-02-13

申请号：US17731994

申请日：2022-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjin Cho ,  Jungmin You

IPC: G11C29/20 ,  G11C29/00 ,  G11C29/44

CPC classification number: G11C29/20 ,  G11C29/4401 ,  G11C29/783 ,  G11C29/787

Abstract: A semiconductor memory device includes a memory cell array including memory cell row, each of which includes volatile memory cells, a row hammer management circuit, a repair control circuit and a connection logic. The row hammer management circuit counts access addresses associated with the memory cell rows to store counting values, and determines a hammer address associated with least one of the memory cell rows, which is intensively accessed, based on the counting values. The repair control circuit includes repair controllers, each of which includes a defective address storage, and repairs a defective memory cell row among the memory cell rows. The connection logic connects first repair controllers, which are unused for storing defective addresses, among the plurality of repair controllers, to the row hammer management circuit. The row hammer management circuit uses the first repair controllers as a storage resource to store a portion of the access addresses.

公开(公告)号：US12056371B2

公开(公告)日：2024-08-06

申请号：US17982099

申请日：2022-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin You ,  Seongjin Cho

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0673

Abstract: The present disclosure provides methods, apparatuses, and systems having reduced power noise in a refresh operation. In some embodiments, an operating method includes: performing, in response to receiving a first refresh command, a first normal refresh, at a first refresh timing, in which first N word lines of a plurality of word lines are simultaneously refreshed, and a first target refresh, at a second refresh timing, on at least one first victim word line that is adjacent to a maximum activated word line that is most frequently activated from among the plurality of word lines; and performing, in response to receiving a second refresh command, a second normal refresh, at a third refresh timing, in which second N word lines are simultaneously refreshed, and a second target refresh, at a fourth refresh timing, on at least one second victim word line that is adjacent to the maximum activated word line.

公开(公告)号：US12236993B2

公开(公告)日：2025-02-25

申请号：US18052469

申请日：2022-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin You

IPC: G11C11/406 ,  G11C11/408

Abstract: Provided are a memory device for detecting a weakness of an operation pattern and a method of operating the same. The method includes: storing address information and activation count information regarding N word lines from among the plurality of word lines in a register including N entries; based on activation of a first word line different from the N word lines, storing address information and activation count information regarding the first word line in an entry from which information is evicted from among the N entries; and generating first weakness information based on a number of evictions performed on the register during a first period.

公开(公告)号：US11967352B2

公开(公告)日：2024-04-23

申请号：US17741604

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin You ,  Wonhyung Song ,  Hoyoun Kim

IPC: G11C11/406 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.

公开(公告)号：US20240096395A1

公开(公告)日：2024-03-21

申请号：US18470471

申请日：2023-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghye Cho ,  Eunae Lee ,  Jungmin You ,  Yeonggeol Song ,  Kyomin Sohn ,  Kijun Lee ,  Myungkyu Lee

IPC: G11C11/406 ,  G11C11/4078

CPC classification number: G11C11/40622 ,  G11C11/40611 ,  G11C11/4078

Abstract: A device, an operating method of a memory controller, a memory device, and a compute express link (CXL) memory expansion device all for managing a row hammer are provided. The device includes a volatile memory and a memory controller that is configured to detect, based on input row addresses, a pattern size of a row hammer attack pattern and a row distribution of row hammer addresses, to determine, according to a type of the row distribution, whether to perform refresh management, and for every L access corresponding to the pattern size, to provide, to the volatile memory, a refresh management command and a target row address, where L is an integer greater than or equal to 1.

公开(公告)号：US20230128653A1

公开(公告)日：2023-04-27

申请号：US17880254

申请日：2022-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin You

IPC: G11C11/406 ,  G11C11/4072

Abstract: Provided are a method for controlling a row hammer and a memory device. The memory device includes: a memory cell array having memory cell rows; a control logic circuit configured to classify access addresses of the memory cell array as real and fake entries, and identify a row hammer address from among the access addresses; and a refresh control circuit configured to refresh a memory cell row physically adjacent to a memory cell row indicated by the row hammer address during a row hammer monitoring time frame. The control logic circuit is further configured to promote a fake entry to a real entry based on the number of accesses of the fake entry being equal to or greater than a first threshold.

公开(公告)号：US12014764B2

公开(公告)日：2024-06-18

申请号：US17939327

申请日：2022-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin You

IPC: G11C11/406 ,  G11C11/4078

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4078

Abstract: A row hammer preventing circuitry including: a first table storing a count value representing a hit count and an address bit of multiple entries, each entry corresponding to access-requested target rows; a second table including safe bits and a safe bit counter; and a row hammer preventing logic to identify masking entries, on which a masking comparison is to be performed, among the entries on the basis of the safe bit counter, to determine a hit or miss on the basis of whether other bits except an MSB among address bits of an access-requested target row match other bits except an MSB among address bits of the masking entries, and to generate a control signal indicating an additional refresh on rows adjacent to rows corresponding to a masking entry whose hit count is greater than a threshold value.

公开(公告)号：US11922989B2

公开(公告)日：2024-03-05

申请号：US17724942

申请日：2022-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin You ,  Seongjin Cho

IPC: G11C11/406 ,  G11C11/4093

CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/40626 ,  G11C11/4093

Abstract: A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.

公开(公告)号：US20230168818A1

公开(公告)日：2023-06-01

申请号：US17982099

申请日：2022-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin You ,  Seongjin Cho

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0673 ,  G06F3/0653

Abstract: The present disclosure provides methods, apparatuses, and systems having reduced power noise in a refresh operation. In some embodiments, an operating method includes: performing, in response to receiving a first refresh command, a first normal refresh, at a first refresh timing, in which first N word lines of a plurality of word lines are simultaneously refreshed, and a first target refresh, at a second refresh timing, on at least one first victim word line that is adjacent to a maximum activated word line that is most frequently activated from among the plurality of word lines; and performing, in response to receiving a second refresh command, a second normal refresh, at a third refresh timing, in which second N word lines are simultaneously refreshed, and a second target refresh, at a fourth refresh timing, on at least one second victim word line that is adjacent to the maximum activated word line.

公开(公告)号：US12236995B2

公开(公告)日：2025-02-25

申请号：US18426503

申请日：2024-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin You ,  Seongjin Cho

IPC: G11C11/406 ,  G11C11/4093

Abstract: A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.