公开(公告)号：US20240030119A1

公开(公告)日：2024-01-25

申请号：US18374396

申请日：2023-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGKYU KIM ,  SEOKHYUN LEE ,  KYOUNG LIM SUK ,  JAEGWON JANG ,  GWANGJAE JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L24/32 ,  H01L24/16 ,  H01L23/49833 ,  H01L25/0657 ,  H01L23/49894 ,  H01L2224/16227 ,  H01L2224/32225

Abstract: A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.

公开(公告)号：US20210375642A1

公开(公告)日：2021-12-02

申请号：US17399941

申请日：2021-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK

IPC: H01L21/48 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package may include a lower re-distribution layer, a stack bonded to a portion of the lower re-distribution layer, a semiconductor chip on a top surface of the lower re-distribution layer, and an upper re-distribution layer on the semiconductor chip and the stack.

公开(公告)号：US20200083201A1

公开(公告)日：2020-03-12

申请号：US16430426

申请日：2019-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK ,  SEOKHYUN LEE

IPC: H01L25/10 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.

公开(公告)号：US20250167098A1

公开(公告)日：2025-05-22

申请号：US19029539

申请日：2025-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYOUNG LIM SUK ,  KEUNG BEUM KIM ,  DONGKYU KIM ,  MINJUNG KIM ,  SEOKHYUN LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

公开(公告)号：US20250070038A1

公开(公告)日：2025-02-27

申请号：US18945235

申请日：2024-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYOUNG LIM SUK ,  SEOKHYUN LEE ,  JAEGWON JANG

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate that has a first trench that extends through a top surface of the redistribution substrate, a first semiconductor chip on the redistribution substrate, a capacitor chip on a bottom surface of the first semiconductor chip, and an under-fill layer on the bottom surface of the first semiconductor chip. The redistribution substrate includes a plurality of dielectric layers vertically stacked, a plurality of redistribution patterns in each of the dielectric layers, and a plurality of dummy redistribution patterns in the first trench. The dummy redistribution patterns vertically overlap the first semiconductor chip. An uppermost surface of the dummy redistribution pattern is located at a level higher than a level of a bottom surface of the first trench.

公开(公告)号：US20230065366A1

公开(公告)日：2023-03-02

申请号：US17806907

申请日：2022-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGKYU KIM ,  MINJUNG KIM ,  KYOUNG LIM SUK ,  SEOKHYUN LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a first redistribution substrate, a passive device mounted on a bottom surface of the first redistribution substrate, a first semiconductor chip disposed on a top surface of the first redistribution substrate, the first semiconductor chip including a through via disposed therein, a second semiconductor chip disposed on the first semiconductor chip, and a conductive post disposed between the top surface of the first redistribution substrate and a bottom surface of the second semiconductor chip and spaced apart from the first semiconductor chip. The conductive post is connected to the first redistribution substrate and to the second semiconductor chip. The conductive post overlaps with at least a portion of the passive device in a vertical direction normal to the top surface of the first redistribution substrate.

公开(公告)号：US20210398890A1

公开(公告)日：2021-12-23

申请号：US17177305

申请日：2021-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGKYU KIM ,  SEOKHYUN LEE ,  KYOUNG LIM SUK ,  JAEGWON JANG ,  GWANGJAE JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.

公开(公告)号：US20210193636A1

公开(公告)日：2021-06-24

申请号：US17179470

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK ,  SEOKHYUN LEE

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/522 ,  H01L23/528

Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.

公开(公告)号：US20250022788A1

公开(公告)日：2025-01-16

申请号：US18666967

申请日：2024-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK ,  HYEONJEONG HWANG ,  Sehoon JANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L25/10

Abstract: An embodiment provides a semiconductor package including: a first redistribution layer structure including a plurality of redistribution vias and a plurality of UBM structures; and a first semiconductor die on the first redistribution layer structure, wherein each of the plurality of UBM structures includes a UBM via; and a UBM wire line extending in a horizontal direction on the UBM via and electrically connecting one of the plurality of redistribution vias and the UBM via in the horizontal direction.

公开(公告)号：US20240178185A1

公开(公告)日：2024-05-30

申请号：US18357484

申请日：2023-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGKYU KIM ,  KYUNG DON MUN ,  KYOUNG LIM SUK ,  HYEONJEONG HWANG

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/0652 ,  H01L23/3736 ,  H01L23/5383 ,  H01L23/5384 ,  H10B80/00

Abstract: Disclosed is a semiconductor package comprising a lower circuit part having a first region and a second region horizontally offset from each other and including a connection structure within the first region and a logic chip within the second region, a memory structure that overlaps the connection structure in a vertical direction, and a thermal radiation structure that overlaps the logic chip in the vertical direction. The logic chip and the memory structure are spaced apart in a horizontal direction parallel to a top surface of the logic chip.