公开(公告)号：US20250022788A1

公开(公告)日：2025-01-16

申请号：US18666967

申请日：2024-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK ,  HYEONJEONG HWANG ,  Sehoon JANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L25/10

Abstract: An embodiment provides a semiconductor package including: a first redistribution layer structure including a plurality of redistribution vias and a plurality of UBM structures; and a first semiconductor die on the first redistribution layer structure, wherein each of the plurality of UBM structures includes a UBM via; and a UBM wire line extending in a horizontal direction on the UBM via and electrically connecting one of the plurality of redistribution vias and the UBM via in the horizontal direction.

公开(公告)号：US20240153906A1

公开(公告)日：2024-05-09

申请号：US18386687

申请日：2023-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byeongtak PARK ,  Gwanghee JO ,  Siwoong WOO ,  Jiwon SON ,  Yongjoo LEE ,  Hoechul KIM ,  Inhwa BAEK ,  Seungdae SEOK ,  Sehoon JANG ,  Jaehyun PHEE

IPC: H01L23/00

CPC classification number: H01L24/74 ,  H01L2224/74 ,  H01L2924/40

Abstract: A substrate bonding apparatus includes a first bonding chuck having a first base, a deformable plate on the first base to support a first substrate, and a lower pressurer under the first base to apply pressure to the deformable plate, and a second bonding chuck vertically spaced apart from the first bonding chuck and having a second base to fix a second substrate, and an upper pressurer to apply pressure to the second substrate. The deformable plate includes an outer portion surrounding a center portion, a bottom surface of the outer portion of the deformable plate being adhered to the first base, the center portion being deformable in the vertical direction by the lower pressurer, and thicknesses of the center and outer portions of the deformable plate in the vertical direction being different from each other.

公开(公告)号：US20250087565A1

公开(公告)日：2025-03-13

申请号：US18588460

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehoon JANG ,  Kyung Don MUN

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00

Abstract: A wiring structure may include a wiring layer including a wiring pad, an insulating layer on the wiring layer and covering the wiring layer, a connection pad on the insulating layer, and a via passing through the insulating layer and connecting the wiring pad and the connection pad. The wiring pad may include a first metal layer and a second metal layer on the first metal layer. A bottom surface of the via may abut the first metal layer, and the second metal layer may surround a side surface of the via and may be adjacent to the bottom surface.

公开(公告)号：US20240242981A1

公开(公告)日：2024-07-18

申请号：US18415798

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehoon JANG ,  Inhwa BAEK ,  Hyungku KIM ,  Kibum YU ,  Jaesung YUN ,  Yongin LEE ,  Jaehyuk JUNG ,  Gwanghee JO ,  Youngjin CHO

IPC: H01L21/67 ,  H01L23/00

CPC classification number: H01L21/67092 ,  H01L24/80 ,  H01L2224/80894

Abstract: A substrate bonding apparatus may include a first bonding chuck including a first base and a first transformation plate, and a second including a second base facing the first bonding chuck. The first base may include a recess groove. The recess groove may be recessed inward from a surface on which the first transformation plate is mounted. The first transformation plate may include a first protrusion protruding outward from a first surface of the first transformation plate. A second surface of the first transformation plate may be opposite the first surface of the first transformation plate. The second surface of the first transformation plate may be configured to support a first substrate. The first transformation plate may be mounted on the first base in a manner allowing a distance between the first transformation plate and the first base to vary.

公开(公告)号：US20240145396A1

公开(公告)日：2024-05-02

申请号：US18381711

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehoon JANG ,  Hyeonjeong HWANG ,  Kyounglim SUK

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5385 ,  H01L25/18 ,  H10B80/00 ,  H01L24/16

Abstract: A semiconductor package includes a base substrate. An interposer substrate includes a plurality of interposer redistribution structures sequentially stacked in a vertical direction and an interposer insulation layer. The plurality of interposer redistribution structures includes a plurality of conductive interposer patterns and a plurality of conductive interposer vias. A semiconductor chip is disposed between the base substrate and the interposer substrate and is attached on the base substrate. A plurality of conductive connection pads is respectively disposed on a plurality of uppermost conductive interposer patterns of an uppermost interposer redistribution structure of the plurality of interposer redistribution structures. The interposer insulation layer includes a plurality of pad holes exposing at least a portion of each of an upper surface of a corresponding uppermost conductive interposer pattern of the plurality of uppermost conductive interposer patterns.

公开(公告)号：US20240047324A1

公开(公告)日：2024-02-08

申请号：US18183699

申请日：2023-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjeong HWANG ,  Dongwook KIM ,  Kyounglim SUK ,  Inhyung SONG ,  Sehoon JANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L24/32 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L24/73 ,  H01L24/05 ,  H01L21/565 ,  H01L23/3128 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/16227 ,  H01L2224/0401 ,  H01L2225/1058 ,  H01L2224/05008

Abstract: A semiconductor package includes a redistribution wiring layer having a first surface and a second surface opposite to the first surface, a conductive bump on the first surface, and a first semiconductor device on the conductive bump. The redistribution wiring layer includes redistribution wirings having an uppermost redistribution wiring, a bonding pad, and an uppermost insulating layer. The uppermost redistribution wiring has a redistribution via and a redistribution line on the redistribution via. The bonding pad disposes on the redistribution line of the uppermost redistribution wiring, and the conductive bump is disposed on the bonding pad. The uppermost insulating layer overlapping (e.g., covering) the uppermost redistribution wiring and having an opening exposing a portion of the bonding pad.