公开(公告)号：US20190180806A1

公开(公告)日：2019-06-13

申请号：US16274860

申请日：2019-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SU YEON DOO ,  SEUNGJUN BAE ,  SIHONG KIM ,  HOSUNG SONG

IPC: G11C8/18 ,  G11C7/22 ,  G11C11/4076 ,  G06F11/10 ,  G11C5/04

CPC classification number: G11C8/18 ,  G06F11/1004 ,  G11C5/04 ,  G11C7/22 ,  G11C11/4076 ,  G11C2029/0411

Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

公开(公告)号：US20190139596A1

公开(公告)日：2019-05-09

申请号：US16032361

申请日：2018-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-soo JANG ,  Eunsung SEO ,  SEUNGJUN BAE

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C7/1063 ,  G11C11/40603 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/40626 ,  G11C11/4087 ,  H04N5/3355

Abstract: A semiconductor memory device includes a cell array that includes a plurality of DRAM cells to store data, and refresh control logic that refreshes the plurality of DRAM cells depending on access scenario information provided from an outside. The refresh control logic determines a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells and refreshes the plurality of DRAM cells depending on the determined refresh time.