公开(公告)号：US20180190341A1

公开(公告)日：2018-07-05

申请号：US15830314

申请日：2017-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-geun DO ,  Jong-ho LEE ,  Chan-yong LEE ,  Min-soo JANG

IPC: G11C11/406 ,  G11C11/4063

CPC classification number: G11C11/40615 ,  G11C11/40618 ,  G11C11/4063 ,  G11C11/4074 ,  G11C2211/4067 ,  G11C2211/4068

Abstract: Provided is a memory device capable of reducing power consumption. The memory device includes a plurality of memory cells; and a self refresh controller configured to perform a refreshing cycle, which includes a first time interval and a second time interval, for a plurality of number of times, the second time interval being longer than the first section, wherein the self refresh controller is configured to perform a burst refreshing operation during the first time interval and to perform a power supply controlling operation during the second time interval.

公开(公告)号：US20190139596A1

公开(公告)日：2019-05-09

申请号：US16032361

申请日：2018-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-soo JANG ,  Eunsung SEO ,  SEUNGJUN BAE

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C7/1063 ,  G11C11/40603 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/40626 ,  G11C11/4087 ,  H04N5/3355

Abstract: A semiconductor memory device includes a cell array that includes a plurality of DRAM cells to store data, and refresh control logic that refreshes the plurality of DRAM cells depending on access scenario information provided from an outside. The refresh control logic determines a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells and refreshes the plurality of DRAM cells depending on the determined refresh time.