公开(公告)号：US20170141092A1

公开(公告)日：2017-05-18

申请号：US15254259

申请日：2016-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoungjoon Kim ,  Kwangil PARK ,  Seok-Hong KWON ,  Chulsung PARK ,  Eunsung SEO ,  Heejin LEE ,  Kijong PARK

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311

Abstract: A semiconductor package includes a logic chip mounted on a substrate, a first memory chip disposed on the logic chip, which includes a first active surface, and a second memory chip disposed on the first memory chip. The second memory chip is disposed on the first memory chip in such a way that the first memory chip and second memory chip are offset from each other. The second memory chip has a second active surface. The first active surface and the second active surface face each other and are electrically connected to each other through a first solder bump.

公开(公告)号：US20190139596A1

公开(公告)日：2019-05-09

申请号：US16032361

申请日：2018-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-soo JANG ,  Eunsung SEO ,  SEUNGJUN BAE

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C7/1063 ,  G11C11/40603 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/40626 ,  G11C11/4087 ,  H04N5/3355

Abstract: A semiconductor memory device includes a cell array that includes a plurality of DRAM cells to store data, and refresh control logic that refreshes the plurality of DRAM cells depending on access scenario information provided from an outside. The refresh control logic determines a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells and refreshes the plurality of DRAM cells depending on the determined refresh time.