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    MEMORY SYSTEM FOR ADJUSTING CLOCK FREQUENCY
    2.
    发明申请
    MEMORY SYSTEM FOR ADJUSTING CLOCK FREQUENCY 审中-公开

    公开(公告)号：US20190180797A1

    公开(公告)日：2019-06-13

    申请号：US16054633

    申请日：2018-08-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YOUNG-JU KIM ,  DONG-SEOK KANG ,  HYE JUNG KWON ,  BYUNGCHUL KIM ,  SEUNGJUN BAE

    IPC: G11C7/10 ,  G11C11/4076 ,  G11C8/18 ,  G11C11/408 ,  G11C11/4096 ,  H03L7/08

    Abstract: A memory system includes a logic circuit and a phase locked loop (PLL) circuit. The logic circuit determines a first frequency of a first clock using a first signal and generates a second signal for adjusting the first frequency of the first clock. The PLL circuit receives a second clock, and generates the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal. When a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.

    OUTPUT CIRCUIT FOR IMPLEMENTING HIGH SPEED DATA TRANSMITION
    4.
    发明申请
    OUTPUT CIRCUIT FOR IMPLEMENTING HIGH SPEED DATA TRANSMITION 有权
    用于实施高速数据传输的输出电路

    公开(公告)号：US20150036448A1

    公开(公告)日：2015-02-05

    申请号：US14322129

    申请日：2014-07-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： MINSU AHN ,  SEUNGJUN BAE ,  JOON-YOUNG PARK ,  YOON-JOO EOM

    IPC: G11C11/4076 ,  G11C11/408

    CPC classification number: G11C11/4076 ,  G11C7/02 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4093

    Abstract: An output circuit includes first and second output drivers. The first output driver is configured to transfer a first data signal directly to an output pad in synchronization with a clock signal. The second output driver is configured to transfer a second data signal directly to the output pad in synchronization with an inversion clock signal. The clock signal and the inversion clock enable multiplexing of the first data signal and the second data signal to provide a multiplexed output data signal.

    Abstract translation: 输出电路包括第一和第二输出驱动器。 第一输出驱动器被配置为与时钟信号同步地将第一数据信号直接传送到输出焊盘。 第二输出驱动器被配置为与反相时钟信号同步地将第二数据信号直接传送到输出焊盘。 时钟信号和反相时钟使第一数据信号和第二数据信号复用，从而提供多路输出数据信号。

    SEMICONDUCTOR MEMORY DEVICE AND DETECTION CLOCK PATTERN GENERATING METHOD THEREOF
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND DETECTION CLOCK PATTERN GENERATING METHOD THEREOF 审中-公开
    半导体存储器件及其检测时钟图案生成方法

    公开(公告)号：US20140086002A1

    公开(公告)日：2014-03-27

    申请号：US13828869

    申请日：2013-03-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SU YEON DOO ,  SEUNGJUN BAE ,  SIHONG KIM ,  HOSUNG SONG

    IPC: G11C8/18

    CPC classification number: G11C8/18 ,  G06F11/1004 ,  G11C5/04 ,  G11C7/22 ,  G11C11/4076 ,  G11C2029/0411

    Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

    Abstract translation: 提供了一种半导体存储器件的时钟图形生成方法。 该方法包括当输出选择控制信号处于第一状态时通过多个检测时钟输出引脚产生相同的时钟模式，并且当输出选择控制信号为 处于与第一状态不同的第二状态。

    MEMORY DEVICE AND DIVIDED CLOCK CORRECTION METHOD THEREOF
    8.
    发明申请
    MEMORY DEVICE AND DIVIDED CLOCK CORRECTION METHOD THEREOF 审中-公开

    公开(公告)号：US20200013441A1

    公开(公告)日：2020-01-09

    申请号：US16571868

    申请日：2019-09-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-Seok Kang ,  SEUNGJUN BAE

    IPC: G11C7/10 ,  H04L25/02 ,  H04L7/08 ,  H04L7/00 ,  H03L7/085 ,  G11C7/22

    Abstract: A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.

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