公开(公告)号：US20250107066A1

公开(公告)日：2025-03-27

申请号：US18643311

申请日：2024-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo Won Yoo ,  Jin Woo Han ,  Seok Han Park ,  Sung-Min Park ,  Gyu Hwan Oh

IPC: H10B12/00 ,  G11C5/06

Abstract: A semiconductor memory device includes a cell region element separation film that is on a substrate and includes first and second cell region side walls; an active pattern that is on the substrate; a word line that is on the first side wall of the active pattern; a back gate electrode that is on the second side wall of the active pattern; a bit line that is electrically connected to the first side of the active pattern; and a data storage pattern that is electrically connected to the second side of the active pattern, where the word line includes an electrode part and a plug connecting part, and where the plug connecting part of the word line includes a first connecting extending part and a second connecting extending part.

公开(公告)号：US11165018B2

公开(公告)日：2021-11-02

申请号：US16592041

申请日：2019-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Hwan Lee ,  Yong Seok Kim ,  Tae Hun Kim ,  Seok Han Park ,  Satoru Yamada ,  Jae Ho Hong

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.

公开(公告)号：US10950510B2

公开(公告)日：2021-03-16

申请号：US16538184

申请日：2019-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Han Park

IPC: H01L23/08 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02

Abstract: A semiconductor device includes a base substrate, a protruding structure on the base substrate, a porous film on a side surface and an upper surface of the protruding structure, and an air gap between at least a part of the side surface of the protruding structure and the porous film.

公开(公告)号：US10916623B2

公开(公告)日：2021-02-09

申请号：US16412961

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Han Park

IPC: H01L49/02 ,  H01L27/108 ,  H01L29/40

Abstract: A semiconductor device including one or more switches on a substrate, a first electrode connected to the one or more switches and having a helical shape defining a spiral groove, a support in contact with the first electrode, the spiral groove extending between the support and a portion of the first electrode, a capacitor dielectric layer in contact with the first electrode, and a second electrode in contact with the capacitor dielectric layer.

公开(公告)号：US10679997B2

公开(公告)日：2020-06-09

申请号：US16391888

申请日：2019-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Wook Jung ,  Dong Oh Kim ,  Seok Han Park ,  Chan Sic Yoon ,  Ki Seok Lee ,  Ho In Lee ,  Ju Yeon Jang ,  Je Min Park ,  Jin Woo Hong

IPC: H01L27/108 ,  H01L21/8238 ,  H01L27/11 ,  H01L27/092 ,  H01L29/10 ,  H01L23/535

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US10573652B2

公开(公告)日：2020-02-25

申请号：US15945401

申请日：2018-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myeong-Dong Lee ,  Jun-Won Lee ,  Ki Seok Lee ,  Bong-Soo Kim ,  Seok Han Park ,  Sung Hee Han ,  Yoo Sang Hwang

IPC: H01L27/108 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.

公开(公告)号：US10325802B2

公开(公告)日：2019-06-18

申请号：US15712410

申请日：2017-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho In Lee ,  Dong Oh Kim ,  Seok Han Park ,  Chan Sic Yoon ,  Ki Wook Jung ,  Jinwoo Augustin Hong ,  Je Min Park ,  Ki Seok Lee ,  Ju Yeon Jang

IPC: H01L21/762 ,  H01L27/108 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L29/43 ,  H01L29/06

Abstract: A method for fabricating a semiconductor device includes forming a device isolation film on a substrate between first and second regions, forming first and second sealing films, such that an etch selectivity of the second sealing film is smaller than that of the first sealing film, patterning the first and second sealing films to expose the second region and a portion of the device isolation film, such that an undercut is defined under a lower surface of the second sealing film, forming a filling film filling the undercut, a thickness of the filling film being thicker on a side surface of the second sealing film than on an upper surface thereof, removing a portion of the filling film to form a filling spacer in the undercut, forming a high-k dielectric film and a metal film on the filling spacer, and patterning the high-k dielectric film and the metal film.