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    Memory device, memory system having the same and method of operating the same
    12.
    发明授权
    Memory device, memory system having the same and method of operating the same 有权

    公开(公告)号：US12236995B2

    公开(公告)日：2025-02-25

    申请号：US18426503

    申请日：2024-01-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungmin You ,  Seongjin Cho

    IPC: G11C11/406 ,  G11C11/4093

    Abstract: A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.

    Memory device, memory system having the same and operating method thereof
    13.
    发明授权
    Memory device, memory system having the same and operating method thereof 有权

    公开(公告)号：US12217786B2

    公开(公告)日：2025-02-04

    申请号：US18613361

    申请日：2024-03-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hijung Kim ,  Hoyoun Kim ,  Jungmin You ,  Seongjin Cho

    IPC: G11C11/00 ,  G06F7/544 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4094

    Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.

    Memory devices and methods for controlling row hammer
    14.
    发明授权
    Memory devices and methods for controlling row hammer 有权

    公开(公告)号：US12119044B2

    公开(公告)日：2024-10-15

    申请号：US18052644

    申请日：2022-11-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seongjin Cho

    IPC: G11C11/40 ,  G11C11/406 ,  G11C11/4078 ,  G11C11/4096

    CPC classification number: G11C11/4078 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4096

    Abstract: Memory devices and methods for controlling a row hammer are provided. The memory device includes a memory cell array including a word line and a plurality of counter memory cells storing an access count value of the word line, and a control logic circuit configured to monitor a row address accessing the word line during a row hammer monitoring time frame and to determine the row address to be a row hammer address when the number of times the word line is accessed is greater than or equal to a threshold value, wherein the row hammer address is to be stored in an address storage. The control logic circuit is further configured to hold up a determination operation for a next row hammer address, based on activation of a latch full signal indicating that there is no free space to store the row hammer address in the address storage.

    MEMORY DEVICE AND METHOD OF CONTROLLING ROW HAMMER
    15.
    发明公开
    MEMORY DEVICE AND METHOD OF CONTROLLING ROW HAMMER 审中-公开

    公开(公告)号：US20240304234A1

    公开(公告)日：2024-09-12

    申请号：US18669714

    申请日：2024-05-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungmin You ,  Seongjin Cho

    IPC: G11C11/408 ,  G11C11/406

    CPC classification number: G11C11/4087 ,  G11C11/406

    Abstract: A method of controlling a row hammer swaps a first address entry with a second address entry having the smallest second access number and randomly swaps the first address entry with a third address entry having a third access number which is not the greatest value, in an address table representing a correlation between an address entry accessed during a row hammer monitoring time frame and an access number, thereby preventing a hacker-pattern row hammer aggression from being easily performed.

    Memory device and method of controlling row hammer
    16.
    发明授权
    Memory device and method of controlling row hammer 有权

    公开(公告)号：US12027199B2

    公开(公告)日：2024-07-02

    申请号：US17707034

    申请日：2022-03-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungmin You ,  Seongjin Cho

    IPC: G11C11/408 ,  G11C11/406

    CPC classification number: G11C11/4087 ,  G11C11/406

    Abstract: A method of controlling a row hammer swaps a first address entry with a second address entry having the smallest second access number and randomly swaps the first address entry with a third address entry having a third access number which is not the greatest value, in an address table representing a correlation between an address entry accessed during a row hammer monitoring time frame and an access number, thereby preventing a hacker-pattern row hammer aggression from being easily performed.

    MEMORY DEVICES AND METHODS FOR CONTROLLING ROW HAMMER
    18.
    发明公开
    MEMORY DEVICES AND METHODS FOR CONTROLLING ROW HAMMER 审中-公开

    公开(公告)号：US20230178140A1

    公开(公告)日：2023-06-08

    申请号：US18052644

    申请日：2022-11-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seongjin Cho

    IPC: G11C11/4078 ,  G11C11/406 ,  G11C11/4096

    CPC classification number: G11C11/4078 ,  G11C11/40622 ,  G11C11/4096 ,  G11C11/40615

    Abstract: Memory devices and methods for controlling a row hammer are provided. The memory device includes a memory cell array including a word line and a plurality of counter memory cells storing an access count value of the word line, and a control logic circuit configured to monitor a row address accessing the word line during a row hammer monitoring time frame and to determine the row address to be a row hammer address when the number of times the word line is accessed is greater than or equal to a threshold value, wherein the row hammer address is to be stored in an address storage. The control logic circuit is further configured to hold up a determination operation for a next row hammer address, based on activation of a latch full signal indicating that there is no free space to store the row hammer address in the address storage.

    MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND METHOD OF OPERATING THE SAME
    19.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20230101739A1

    公开(公告)日：2023-03-30

    申请号：US17724942

    申请日：2022-04-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungmin YOU ,  Seongjin Cho

    IPC: G11C11/406 ,  G11C11/4093

    Abstract: A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.

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