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    BIT LINE SENSE AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME
    2.
    发明申请
    BIT LINE SENSE AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20240379151A1

    公开(公告)日：2024-11-14

    申请号：US18784746

    申请日：2024-07-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seongjin Cho

    IPC: G11C11/4091 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

    Abstract: A bit line sense amplifier includes a first inverter having an output terminal connected to a complementary sensing bit line, a second inverter having an output terminal connected to a sensing bit line, a first offset element connecting a bit line to the complementary sensing bit line and a second offset element connecting a complementary bit line to the sensing bit line, in response to an offset cancellation signal. During a first time interval, the first offset element and the second offset element are turned off and a capacitor of a first memory cell is connected to the bit line. During a second time interval after the first time interval, the first offset element and the second offset element are turned on and the capacitor of the first memory cell is disconnected from the bit line.

    Memory device having reduced power noise in refresh operation and operating method thereof
    3.
    发明授权
    Memory device having reduced power noise in refresh operation and operating method thereof 有权

    公开(公告)号：US12056371B2

    公开(公告)日：2024-08-06

    申请号：US17982099

    申请日：2022-11-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungmin You ,  Seongjin Cho

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0673

    Abstract: The present disclosure provides methods, apparatuses, and systems having reduced power noise in a refresh operation. In some embodiments, an operating method includes: performing, in response to receiving a first refresh command, a first normal refresh, at a first refresh timing, in which first N word lines of a plurality of word lines are simultaneously refreshed, and a first target refresh, at a second refresh timing, on at least one first victim word line that is adjacent to a maximum activated word line that is most frequently activated from among the plurality of word lines; and performing, in response to receiving a second refresh command, a second normal refresh, at a third refresh timing, in which second N word lines are simultaneously refreshed, and a second target refresh, at a fourth refresh timing, on at least one second victim word line that is adjacent to the maximum activated word line.

    MEMORY DEVICE HAVING REDUCED POWER NOISE IN REFRESH OPERATION AND OPERATING METHOD THEREOF
    5.
    发明公开
    MEMORY DEVICE HAVING REDUCED POWER NOISE IN REFRESH OPERATION AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20230168818A1

    公开(公告)日：2023-06-01

    申请号：US17982099

    申请日：2022-11-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungmin You ,  Seongjin Cho

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0673 ,  G06F3/0653

    Abstract: The present disclosure provides methods, apparatuses, and systems having reduced power noise in a refresh operation. In some embodiments, an operating method includes: performing, in response to receiving a first refresh command, a first normal refresh, at a first refresh timing, in which first N word lines of a plurality of word lines are simultaneously refreshed, and a first target refresh, at a second refresh timing, on at least one first victim word line that is adjacent to a maximum activated word line that is most frequently activated from among the plurality of word lines; and performing, in response to receiving a second refresh command, a second normal refresh, at a third refresh timing, in which second N word lines are simultaneously refreshed, and a second target refresh, at a fourth refresh timing, on at least one second victim word line that is adjacent to the maximum activated word line.

    Electronic device including secure integrated circuit
    6.
    发明授权
    Electronic device including secure integrated circuit 有权

    公开(公告)号：US11461475B2

    公开(公告)日：2022-10-04

    申请号：US16815541

    申请日：2020-03-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Bumhan Kim ,  Sunjune Kong ,  Seongjin Cho

    IPC: G06F21/60 ,  G06F7/58 ,  G06F12/14 ,  G06F15/78 ,  H01L23/00 ,  H04L9/08

    Abstract: An electronic device including a secure Integrated Circuit (IC) is provided. The electronic device includes a secure IC configured as a System-on-Chip (SoC) and configured to provide a general environment and a security environment, wherein the secure IC includes a main processor configured to operate in the general environment, a secure processor configured to operate in the security environment and control security of data using a first security key, and a secure memory configured to be operatively connected to the secure processor and store a second security key corresponding to the first security key. Various other embodiments are possible.

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12236998B2

    公开(公告)日：2025-02-25

    申请号：US18143127

    申请日：2023-05-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seongjin Cho ,  Kyuchang Kang ,  Keonwoo Park ,  Donghak Shin

    IPC: G11C11/40 ,  G11C11/408 ,  G11C11/4091 ,  H01L25/065 ,  H10B12/00 ,  H10B80/00

    Abstract: A semiconductor device includes a memory cell array that includes a plurality of memory cells electrically connected to a plurality of word lines and a plurality of bit lines, a word line driving circuit that includes a plurality of sub-word line decoders electrically connected to the plurality of word lines, and a control logic configured to determine a selected word line and unselected word lines among the plurality of word lines, and configured to control the word line driving circuit such that at least one of the unselected word lines that is adjacent to the selected word line is floated during at least a portion of a period in which a voltage of the selected word line returns to an initial level.

    Bit line sense amplifier and memory device including the same
    8.
    发明授权
    Bit line sense amplifier and memory device including the same 有权

    公开(公告)号：US12087351B2

    公开(公告)日：2024-09-10

    申请号：US17857015

    申请日：2022-07-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seongjin Cho

    IPC: G11C7/00 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

    CPC classification number: G11C11/4091 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096

    Abstract: A bit line sense amplifier includes a first inverter having an output terminal connected to a complementary sensing bit line, a second inverter having an output terminal connected to a sensing bit line, a first offset element connecting a bit line to the complementary sensing bit line and a second offset element connecting a complementary bit line to the sensing bit line, in response to an offset cancellation signal. During a first time interval, the first offset element and the second offset element are turned off and a capacitor of a first memory cell is connected to the bit line. During a second time interval after the first time interval, the first offset element and the second offset element are turned on and the capacitor of the first memory cell is disconnected from the bit line.

    Semiconductor memory device and method of operating semiconductor memory device
    9.
    发明授权
    Semiconductor memory device and method of operating semiconductor memory device 有权

    公开(公告)号：US11901025B2

    公开(公告)日：2024-02-13

    申请号：US17731994

    申请日：2022-04-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seongjin Cho ,  Jungmin You

    IPC: G11C29/20 ,  G11C29/00 ,  G11C29/44

    CPC classification number: G11C29/20 ,  G11C29/4401 ,  G11C29/783 ,  G11C29/787

    Abstract: A semiconductor memory device includes a memory cell array including memory cell row, each of which includes volatile memory cells, a row hammer management circuit, a repair control circuit and a connection logic. The row hammer management circuit counts access addresses associated with the memory cell rows to store counting values, and determines a hammer address associated with least one of the memory cell rows, which is intensively accessed, based on the counting values. The repair control circuit includes repair controllers, each of which includes a defective address storage, and repairs a defective memory cell row among the memory cell rows. The connection logic connects first repair controllers, which are unused for storing defective addresses, among the plurality of repair controllers, to the row hammer management circuit. The row hammer management circuit uses the first repair controllers as a storage resource to store a portion of the access addresses.

    BIT LINE SENSE AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME
    10.
    发明申请
    BIT LINE SENSE AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20230121199A1

    公开(公告)日：2023-04-20

    申请号：US17857015

    申请日：2022-07-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seongjin Cho

    IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/408

    Abstract: A bit line sense amplifier includes a first inverter having an output terminal connected to a complementary sensing bit line, a second inverter having an output terminal connected to a sensing bit line, a first offset element connecting a bit line to the complementary sensing bit line and a second offset element connecting a complementary bit line to the sensing bit line, in response to an offset cancellation signal. During a first time interval, the first offset element and the second offset element are turned off and a capacitor of a first memory cell is connected to the bit line. During a second time interval after the first time interval, the first offset element and the second offset element are turned on and the capacitor of the first memory cell is disconnected from the bit line.

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