公开(公告)号：US12199096B2

公开(公告)日：2025-01-14

申请号：US18436812

申请日：2024-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Seok Ha ,  Hyun Seung Song ,  Hyo Jin Kim ,  Kyoung Mi Park ,  Guk Il An

IPC: H01L21/00 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

公开(公告)号：US11387345B2

公开(公告)日：2022-07-12

申请号：US17176226

申请日：2021-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guk Il An ,  Keun Hwi Cho ,  Dae Won Ha ,  Seung Seok Ha

IPC: H01L29/51 ,  H01L23/522 ,  H01L27/088 ,  H01L29/78 ,  H01L49/02

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

公开(公告)号：US10916534B2

公开(公告)日：2021-02-09

申请号：US16395691

申请日：2019-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Seok Ha ,  Kyoung-Mi Park ,  Hyun-Seung Song ,  Keon Yong Cheon ,  Dae Won Ha

IPC: H01L27/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

Abstract: A semiconductor device includes a first fin pattern and a second fin pattern in a NMOS region, each extending lengthwise along a first direction and separated by a first trench and a third fin pattern and a fourth fin pattern in a PMOS region, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench. First and second isolation layers are disposed in the first and second trenches, respectively. A first gate electrode extends lengthwise along a second direction transverse to the first direction and crosses the first fin pattern. A second gate electrode extends lengthwise along the second direction and crosses the second fin pattern. Spaced apart third and fourth gate electrodes extend lengthwise along the second direction on the second isolation layer.