公开(公告)号：US11380791B2

公开(公告)日：2022-07-05

申请号：US16225122

申请日：2018-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Hyo-Jin Kim ,  Kyoung-Mi Park ,  Hwi-Chan Jun ,  Seung-Seok Ha

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

Abstract: A semiconductor device includes a first impurity region, a channel pattern, a second impurity region, a gate structure, a first contact pattern, a second contact pattern and a spacer. The first impurity region may be formed on a substrate. The channel pattern may protrude from an upper surface of the substrate. The second impurity region may be formed on the channel pattern. The gate structure may be formed on a sidewall of the channel pattern and the substrate adjacent to the channel pattern, and the gate structure may include a gate insulation pattern and a gate electrode. The first contact pattern may contact an upper surface of the second impurity region. The second contact pattern may contact a surface of the gate electrode. The spacer may be formed between the first and second contact patterns. The spacer may surround a portion of a sidewall of the second contact pattern, and the spacer may contact a sidewall of each of the first and second contact patterns.

公开(公告)号：US12249648B2

公开(公告)日：2025-03-11

申请号：US17857608

申请日：2022-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Seung Song ,  Hyo-Jin Kim ,  Kyoung-Mi Park ,  Hwi-Chan Jun ,  Seung-Seok Ha

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a first impurity region on a substrate; a channel pattern protruding from an upper surface of the substrate, the channel pattern extending in a first direction substantially parallel to the upper surface of the substrate; a second impurity region on the channel pattern, the second impurity region covering an entire upper surface of the channel pattern; a gate structure on a sidewall of the channel pattern and the substrate adjacent to the channel pattern; a first contact pattern on the second impurity region; a second contact pattern that is electrically connected to the gate structure; and a spacer between the first contact pattern and the second contact pattern. The spacer completely surrounds the second contact pattern in plan view, and the first contact pattern partially surrounds the second contact pattern in plan view.

公开(公告)号：US10916534B2

公开(公告)日：2021-02-09

申请号：US16395691

申请日：2019-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Seok Ha ,  Kyoung-Mi Park ,  Hyun-Seung Song ,  Keon Yong Cheon ,  Dae Won Ha

IPC: H01L27/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

Abstract: A semiconductor device includes a first fin pattern and a second fin pattern in a NMOS region, each extending lengthwise along a first direction and separated by a first trench and a third fin pattern and a fourth fin pattern in a PMOS region, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench. First and second isolation layers are disposed in the first and second trenches, respectively. A first gate electrode extends lengthwise along a second direction transverse to the first direction and crosses the first fin pattern. A second gate electrode extends lengthwise along the second direction and crosses the second fin pattern. Spaced apart third and fourth gate electrodes extend lengthwise along the second direction on the second isolation layer.