公开(公告)号：US10957795B2

公开(公告)日：2021-03-23

申请号：US16845591

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Hee Park ,  Myung Gil Kang ,  Young-Seok Song ,  Keon Yong Cheon

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L27/12

Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.

公开(公告)号：US09905645B2

公开(公告)日：2018-02-27

申请号：US15256136

申请日：2016-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Gil Kang ,  Seung Han Park ,  Yong Hee Park ,  Sang Hoon Baek ,  Sang Woo Lee ,  Keon Yong Cheon ,  Sung Man Whang

IPC: H01L21/336 ,  H01L29/778 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L29/41741 ,  H01L29/41758 ,  H01L29/42376 ,  H01L29/7827 ,  H01L29/7851

Abstract: A vertical field effect transistor is provided as follows. A substrate has a lower drain and a lower source arranged along a first direction in parallel to an upper surface of the substrate. A fin structure is disposed on the substrate and extended vertically from the upper surface of the substrate. The fin structure includes a first end portion and a second end portion arranged along the first direction. A bottom surface of a first end portion of the fin structure and a bottom surface of a second end portion of the fin structure overlap the lower drain and the lower source, respectively. The fin structure includes a sidewall having a lower sidewall region, a center sidewall region and an upper sidewall region. A gate electrode surrounds the center side sidewall region of the fin structure.

公开(公告)号：US10665702B2

公开(公告)日：2020-05-26

申请号：US16151511

申请日：2018-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Ill Seo Kang ,  Yong Hee Park ,  Sang Hoon Baek ,  Keon Yong Cheon

IPC: H01L29/66 ,  H01L29/732 ,  H01L27/082 ,  H01L29/06 ,  H01L29/08 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L21/308 ,  H01L29/10 ,  H01L27/06 ,  H01L21/8249 ,  H01L21/8238

Abstract: A vertical bipolar transistor including a substrate including a first well of a first conductivity type and a second well of a second conductivity type different from the first conductivity type, the first well adjoining the second well, a first fin extending, from the first well, a second fin extending from the first well, a third fin extending from the second well, a first conductive region on the first fin, having the second conductivity type and configured to serve as an emitter of the vertical bipolar transistor, a second conductive region on the second fin, having the first conductivity type, and configured to serve as a base of the vertical bipolar transistor, and a third conductive region on the third fin, having the second conductivity type, and configured to serve as a collector of the vertical bipolar transistor may be provided.

公开(公告)号：US10916534B2

公开(公告)日：2021-02-09

申请号：US16395691

申请日：2019-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Seok Ha ,  Kyoung-Mi Park ,  Hyun-Seung Song ,  Keon Yong Cheon ,  Dae Won Ha

IPC: H01L27/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

Abstract: A semiconductor device includes a first fin pattern and a second fin pattern in a NMOS region, each extending lengthwise along a first direction and separated by a first trench and a third fin pattern and a fourth fin pattern in a PMOS region, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench. First and second isolation layers are disposed in the first and second trenches, respectively. A first gate electrode extends lengthwise along a second direction transverse to the first direction and crosses the first fin pattern. A second gate electrode extends lengthwise along the second direction and crosses the second fin pattern. Spaced apart third and fourth gate electrodes extend lengthwise along the second direction on the second isolation layer.

公开(公告)号：US20170033107A1

公开(公告)日：2017-02-02

申请号：US15159978

申请日：2016-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Hak HONG ,  Sungil Park ,  Toshinori Fukai ,  Shigenobu Maeda ,  Sada-aki Masuoka ,  Sanghyun Lee ,  Keon Yong Cheon ,  Hock-Chun Chin

IPC: H01L27/092 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/78 ,  H01L29/7846 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including at least one metal-oxide-semiconductor field-effect transistor (MOSFET) region defined by a device isolation layer and having an active pattern extending in a first direction on the MOSFET region, a gate electrode intersecting the active pattern on the substrate and extending in a second direction intersecting the first direction, and a first gate separation pattern adjacent to the MOSFET region when viewed from a plan view and dividing the gate electrode into segments spaced apart from each other in the second direction. The first gate separation pattern has a tensile strain when the MOSFET region is a P-channel. MOSFET (PMOSFET) region. The first gate separation pattern has a compressive strain when the MOSFET region is an N-channel MOSFET (NMOSFET) region.

Abstract translation: 半导体器件包括：衬底，其包括由器件隔离层限定的至少一个金属氧化物半导体场效应晶体管（MOSFET）区域，并且具有在MOSFET区域上沿第一方向延伸的有源图案;栅极电极与有源 并且沿与第一方向相交的第二方向延伸，以及从平面图观察与MOSFET区域相邻的第一栅极分离图案，并且将栅电极在第二方向上彼此间隔开。 当MOSFET区域为P沟道时，第一栅极分离图案具有拉伸应变。 MOSFET（PMOSFET）区域。 当MOSFET区域是N沟道MOSFET（NMOSFET）区域时，第一栅极分离图案具有压缩应变。