公开(公告)号：US12175299B2

公开(公告)日：2024-12-24

申请号：US17223139

申请日：2021-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Jae-Eon Jo ,  Hyung-Dal Kwon ,  Hanmin Park ,  Jaehyeong Sim ,  Seung Wook Lee

IPC: G06F9/50 ,  G06F1/3237 ,  G06F9/48 ,  G06N3/045 ,  G06N3/063

Abstract: A computing device and method is disclosed. The computing device includes a plurality of processing cores, and a tile scheduler configured to update a cost matrix of each of the plurality of processing cores based on meta information of each of first tiles previously allocated to the plurality of processing cores and meta information of each of second tiles, and allocate the second tiles with respect to the plurality of processing cores using the updated cost matrix of each of the plurality of processing cores.

公开(公告)号：US12052822B2

公开(公告)日：2024-07-30

申请号：US17375307

申请日：2021-07-14

Applicant: Samsung Electronics Co., Ltd. ,  SNU R&DB Foundation

Inventor： Seung Wook Lee ,  Jangwoo Kim ,  Pyeongsu Park

IPC: G06F9/54 ,  G06F9/50 ,  H05K1/02 ,  H05K1/14

CPC classification number: H05K1/14 ,  G06F9/5027 ,  G06F9/54 ,  H05K1/0213 ,  H05K2201/047

Abstract: An electronic device includes: a host box comprising a host processor configured to control an operation of the electronic device, a host motherboard in which the host processor is disposed, and a host power supply unit (PSU) configured to supply power to a component connected to the host motherboard; and one or more extension boxes controlled by the host box, wherein each of the one or more extension boxes comprises an extension motherboard independent of the host box, and an extension PSU independent of the host box and configured to supply power to a component connected to the extension motherboard.

公开(公告)号：US11899741B2

公开(公告)日：2024-02-13

申请号：US16856380

申请日：2020-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-Dal Kwon ,  Seung Wook Lee

IPC: G06F17/15 ,  G06F7/544 ,  G06F17/14 ,  G06F17/16 ,  G06F13/28 ,  H03H17/02

CPC classification number: G06F17/15 ,  G06F7/5443 ,  G06F13/28 ,  G06F17/14 ,  G06F17/16 ,  H03H17/0213

Abstract: A memory device includes a memory configured to store input data and filter data for a convolution operation, and a function processor configured to, in response to a read command of at least a portion of data from among the input data and the filter data, transform the at least a portion of the data based on a parameter of the convolution operation during a clock cycle corresponding to the read command and output a corresponding transformation result as transformed data.

公开(公告)号：US11726929B2

公开(公告)日：2023-08-15

申请号：US17165018

申请日：2021-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SNU R&DB FOUNDATION

Inventor： Seung Wook Lee ,  Soojung Ryu ,  Jintaek Kang ,  Sunjung Lee

IPC: G06F12/02 ,  G06F13/16 ,  G06F7/544 ,  G06F13/28 ,  G06N3/04 ,  G06N3/10

CPC classification number: G06F13/1668 ,  G06F7/5443 ,  G06F13/28 ,  G06N3/04 ,  G06N3/10

Abstract: An accelerator, an operation method of the accelerator, and an accelerator system including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned by a host controller, determining reuse data of the workloads based on hardware resource information and/or a memory access cost of the accelerator when a plurality of processing units included in the accelerator performs the workloads, and providing a result of performing the workloads.

公开(公告)号：US11436168B2

公开(公告)日：2022-09-06

申请号：US17192032

申请日：2021-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SNU R&DB FOUNDATION

Inventor： Seung Wook Lee ,  Hweesoo Kim ,  Jung Ho Ahn

IPC: G06F13/16 ,  G06F15/80

Abstract: An accelerator includes: a memory configured to store input data; a plurality of shift buffers each configured to shift input data received sequentially from the memory in each cycle, and in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array; a plurality of backup buffers each configured to store input data received sequentially from the memory and transfer the stored input data to one of the shift buffers; and the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.