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公开(公告)号：US11720405B2
公开(公告)日：2023-08-08
申请号：US17145958
申请日：2021-01-11
Inventor： Wookeun Jung , Jaejin Lee , Seung Wook Lee
CPC classification number: G06F9/5027 , G06F9/30014 , G06F9/3802 , G06F9/3836 , G06F9/48 , G06N3/063
Abstract: A processor-implemented accelerator method includes: reading, from a memory, an instruction to be executed in an accelerator; reading, from the memory, input data based on the instruction; and performing, on the input data and a parameter value included in the instruction, an inference task corresponding to the instruction.
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公开(公告)号：US12099869B2
公开(公告)日：2024-09-24
申请号：US17195748
申请日：2021-03-09
Applicant: Samsung Electronics Co., Ltd , SNU R&DB FOUNDATION
Inventor： Seung Wook Lee , Younghwan Oh , Jaewook Lee , Sam Son , Yunho Jin , Taejun Ham
CPC classification number: G06F9/4881 , G06F9/5038 , G06F9/505
Abstract: A scheduler, a method of operating the scheduler, and an electronic device including the scheduler are disclosed. The method of operating the scheduler configured to determine a model to be executed in an accelerator includes receiving one or more requests for execution of a plurality of models to be independently executed in the accelerator, and performing layer-wise scheduling on the models based on an idle time occurring when a candidate layer which is a target for the scheduling in each of the models is executed in the accelerator.
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公开(公告)号：US20150019196A1
公开(公告)日：2015-01-15
申请号：US14376612
申请日：2013-01-30
Applicant: Samsung Electronics Co., Ltd
Inventor： Hyun Woo Sim , Hyuk Min Kwon , Seung Wook Lee , Han Su Cho
CPC classification number: G06F9/3001 , G06F9/30181 , G06F9/3889 , G06F9/3897 , G06F9/52 , G06F17/5009 , G06F17/5022 , G06F17/5045 , G06F2217/68
Abstract: In order to achieve tasks, according to an embodiment of the present invention, an arithmetic unit including one or more ASIPs includes two or more processors, and an execution unit that is connected to the two or more processors and executes instructions received from the processors. According to an embodiment of the present invention, it is possible to provide a low-power, high-integration, high-performance arithmetic unit through resource sharing using the arithmetic unit including the one or more ASIPs, and it is possible to provide a method of designing an arithmetic unit that may be applied to a specific application.
Abstract translation: 为了实现任务，根据本发明的实施例，包括一个或多个ASIP的算术单元包括两个或更多个处理器，以及连接到两个或更多个处理器并执行从处理器接收的指令的执行单元。 根据本发明的实施例，可以通过使用包括一个或多个ASIP的算术单元通过资源共享来提供低功率，高集成度的高性能算术单元，并且可以提供一种方法 设计可应用于特定应用的算术单元。
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公开(公告)号：US20140359184A1
公开(公告)日：2014-12-04
申请号：US14356128
申请日：2012-11-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byoung Ik Kang , Joong Baik Kim , Seung Wook Lee
IPC: G06F13/26
CPC classification number: G06F13/26 , G06F9/4812 , G06F9/5083 , G06F2213/2414
Abstract: The present disclosure relates to a method and an apparatus for allocating interruptions in a multi-core system. A method for allocating interruptions in a multi-core system according to one embodiment of the present disclosure comprises: an interrupt load extraction step of extracting interrupt loads of each interruption type; a step of extracting task loads of each core; a weighting factor determination step of determining weighting factors using a difference between task loads of the cores; a step of reflecting weighting factors to extract a converted value of the interrupt load; and an interruption allocation step of allocating interruption types to the cores such that the sums of the converted values of the interrupt loads allocated to each core and the allocated task loads are uniform. According to one embodiment of the present disclosure, interruptions can be allocated such that both task processing and interruption processing can be performed in an efficient manner.
Abstract translation: 本公开涉及一种用于在多核系统中分配中断的方法和装置。 根据本公开的一个实施例的用于在多核系统中分配中断的方法包括：中断负载提取步骤，提取每个中断类型的中断负载; 提取每个核心的任务负载的步骤; 加权因子确定步骤，使用核心的任务负载之间的差来确定加权因子; 反映加权因子以提取中断负载的转换值的步骤; 以及中断分配步骤，用于向核心分配中断类型，使得分配给每个核心的中断负载的转换值和所分配的任务负载之和是均匀的。 根据本公开的一个实施例，可以分配中断，使得可以以有效的方式执行任务处理和中断处理。
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5.发明授权公开(公告)号：US12217085B2
公开(公告)日：2025-02-04
申请号：US17402848
申请日：2021-08-16
Inventor： Seung Wook Lee , Jangwoo Kim , Pyeongsu Park
Abstract: An electronic device includes: a host processor configured to control an operation of the electronic device; accelerators of heterogeneous hardware types configured to exchange data with each other through direct communication; and a control unit configured to convert a command received from the host processor, based on a type of each of the accelerators and transfer a result of the converting to a corresponding accelerator among the accelerators.
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Patent Agency Ranking
公开(公告)号：US12174761B2
公开(公告)日：2024-12-24
申请号：US18212979
申请日：2023-06-22
Applicant: SAMSUNG ELECTRONICS CO., LTD. , SNU R&DB FOUNDATION
Inventor： Seung Wook Lee , Soojung Ryu , Jintaek Kang , Sunjung Lee
Abstract: An accelerator, an operation method of the accelerator, and an accelerator system including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned on an accelerator, determining reuse data of the workloads based on hardware resource information and/or a memory access cost of the accelerator when a plurality of processing units included in the accelerator performs the workloads, and providing a result of performing the workloads.
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公开(公告)号：US11966344B2
公开(公告)日：2024-04-23
申请号：US17876116
申请日：2022-07-28
Applicant: SAMSUNG ELECTRONICS CO., LTD. , SNU R&DB FOUNDATION
Inventor： Seung Wook Lee , Hweesoo Kim , Jung Ho Ahn
CPC classification number: G06F13/1668 , G06F15/8038
Abstract: An accelerator includes: a memory configured to store input data; a plurality of shift buffers each configured to shift input data received sequentially from the memory in each cycle, and in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array; a plurality of backup buffers each configured to store input data received sequentially from the memory and transfer the stored input data to one of the shift buffers; and the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.
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公开(公告)号：US09626314B2
公开(公告)日：2017-04-18
申请号：US14356128
申请日：2012-11-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byoung Ik Kang , Joong Baik Kim , Seung Wook Lee
CPC classification number: G06F13/26 , G06F9/4812 , G06F9/5083 , G06F2213/2414
Abstract: The present disclosure relates to a method and an apparatus for allocating interruptions in a multi-core system. A method for allocating interruptions in a multi-core system according to one embodiment of the present disclosure comprises: an interrupt load extraction step of extracting interrupt loads of each interruption type; a step of extracting task loads of each core; a weighting factor determination step of determining weighting factors using a difference between task loads of the cores; a step of reflecting weighting factors to extract a converted value of the interrupt load; and an interruption allocation step of allocating interruption types to the cores such that the sums of the converted values of the interrupt loads allocated to each core and the allocated task loads are uniform. According to one embodiment of the present disclosure, interruptions can be allocated such that both task processing and interruption processing can be performed in an efficient manner.
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公开(公告)号：US09608024B2
公开(公告)日：2017-03-28
申请号：US14872691
申请日：2015-10-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seung Wook Lee , Yi Tae Kim , Jong Eun Park , Jung Chak Ahn , Kyung Ho Lee , Tae Hun Lee , Hee Geun Jeong
IPC: H01L31/062 , H01L31/113 , H01L27/146 , H04N5/374 , H04N9/04
CPC classification number: H01L27/1463 , H01L27/14603 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14689 , H04N5/374 , H04N9/045
Abstract: An image sensor such as a complementary metal-oxide-semiconductor (CMOS) image sensor and a method of manufacturing the same are provided. The CMOS image sensor includes: a semiconductor substrate including a first surface and a third surface formed by removing a part of the semiconductor substrate from a second surface opposite to the first surface; a plurality of active regions which are formed between the first surface and the third surface and each of which includes a photoelectric conversion element generating charges in response to light input through the third surface; and an isolation region vertically formed from either of the first and third surfaces to isolate the active regions from one another. When the CMOS image sensor is viewed from the above of the third surface, each of the active regions may have round corners and concave sides.
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公开(公告)号：US12277440B2
公开(公告)日：2025-04-15
申请号：US17170109
申请日：2021-02-08
Inventor： Seung Wook Lee , Jae Wook Lee , Young Hwan Oh , Seng Hak Kim , Tae Jun Ham
Abstract: A scheduler, a method of operating the scheduler, and an accelerator apparatus including the scheduler are disclosed. A method of operating a scheduler to perform scheduling on models to be executed in an accelerator, the method includes receiving at least one execution request for a first model and a second model that are executed independently from each other in the accelerator, and performing layer-unit scheduling on the first model and the second model based on workload characteristics of the first model and the second model.
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