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公开(公告)号：US20230318539A1
公开(公告)日：2023-10-05
申请号：US18207066
申请日：2023-06-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Che-Chun Kuo , Siu-Chuang Ivan Lu , Sang Won Son , Xiaohua Yu
Abstract: A wide band matching network for power amplifier impedance matching, the wide band matching network comprising: a power amplifier transistor connected to an output network; the output network including: a series capacitor; an on-chip transformer connected to the capacitor in series, wherein the transformer and the capacitor act as a second order filter; and a port connected to the capacitor and a receiver switch.
MJC/ll-
公开(公告)号：US20230261651A1
公开(公告)日：2023-08-17
申请号：US18301184
申请日：2023-04-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Amitoj Singh , Tienyu Chang , Siu-Chuang Ivan Lu
CPC classification number: H03K17/56 , H03F3/245 , H04B1/04 , H03F2200/451 , H03K2217/0036
Abstract: A shunt switch. In some embodiments, the shunt switch includes a transistor stack including a first transistor and a capacitor. The transistor stack may have a first end terminal and a second end terminal, the first transistor being connected to the first end terminal, the first end terminal being connected to a switching terminal of the shunt switch. The capacitor may have a first terminal connected to the second end terminal of the transistor stack, and a second terminal connected to a low-impedance node.
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公开(公告)号：US12261574B2
公开(公告)日：2025-03-25
申请号：US18207066
申请日：2023-06-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Che-Chun Kuo , Siu-Chuang Ivan Lu , Sang Won Son , Xiaohua Yu
Abstract: A wide band matching network for power amplifier impedance matching, the wide band matching network comprising: a power amplifier transistor connected to an output network; the output network including: a series capacitor; an on-chip transformer connected to the capacitor in series, wherein the transformer and the capacitor act as a second order filter; and a port connected to the capacitor and a receiver switch.
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Patent Agency Ranking
14.发明授权公开(公告)号：US12113301B2
公开(公告)日：2024-10-08
申请号：US17235415
申请日：2021-04-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Venumadhav Bhagavatula , Siu-Chuang Ivan Lu , Sang Won Son
Abstract: A radio frequency integrated circuit (RFIC) and method of communication are provided. The RFIC includes phased-locked loop (PLL) and data stream circuitry and a plurality of tiles in communication with the PLL and data stream circuitry. The plurality of tiles includes comprising at least one tile for each frequency band of the RFIC. The plurality of tiles are configured to communicate a data stream signal between tiles in a cascading sequence. Each tile of the plurality of tiles includes a plurality of up/down conversion mixers for converting the data stream signal between an intermediate frequency (IF) and a radio frequency (RF). Each tile also includes a plurality of front end (FE) elements, each in communication with a corresponding antenna and an up/down conversion mixer of the plurality of up/down conversion mixers.
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公开(公告)号：US12028058B2
公开(公告)日：2024-07-02
申请号：US18301184
申请日：2023-04-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Amitoj Singh , Tienyu Chang , Siu-Chuang Ivan Lu
CPC classification number: H03K17/56 , H03F3/245 , H04B1/04 , H03F2200/451 , H03K2217/0036
Abstract: A shunt switch. In some embodiments, the shunt switch includes a transistor stack including a first transistor and a capacitor. The transistor stack may have a first end terminal and a second end terminal, the first transistor being connected to the first end terminal, the first end terminal being connected to a switching terminal of the shunt switch. The capacitor may have a first terminal connected to the second end terminal of the transistor stack, and a second terminal connected to a low-impedance node.
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公开(公告)号：US11695614B2
公开(公告)日：2023-07-04
申请号：US17064598
申请日：2020-10-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Elina Nayebi , Pranav Dayal , Kee-Bong Song , Siu-Chuang Ivan Lu , Sang Won Son
IPC: H04L27/36 , H04L27/38 , H04L27/148 , H04L27/26 , H04L27/20
CPC classification number: H04L27/364 , H04L27/148 , H04L27/2003 , H04L27/2695 , H04L27/3863
Abstract: A method of compensating for IQ mismatch (IQMM) in a transceiver may include sending first and second signals from a transmit path through a loopback path, using a phase shifter to introduce a phase shift in at least one of the first and second signals, to obtain first and second signals received by a receive path, using the first and second signals received by the receive path to obtain joint estimates of transmit and receive IQMM, at least in part, by estimating the phase shift, and compensating for IQMM using the estimates of IQMM. Using the first and second signals received by the receive path to obtain estimates of the IQMM may include processing the first and second signals received by the receive path as a function of one or more frequency-dependent IQMM parameters.
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公开(公告)号：US11689162B2
公开(公告)日：2023-06-27
申请号：US17111337
申请日：2020-12-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Che-Chun Kuo , Siu-Chuang Ivan Lu , Sang Won Son , Xiaohua Yu
CPC classification number: H03F1/565 , H03F3/245 , H03F2200/06 , H03F2200/165 , H03F2200/222 , H04B1/04
Abstract: A wide band matching network for power amplifier impedance matching, the wide band matching network comprising: a power amplifier transistor connected to an output network; the output network including: a series capacitor; an on-chip transformer connected to the capacitor in series, wherein the transformer and the capacitor act as a second order filter; and a port connected to the capacitor and a receiver switch.
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公开(公告)号：US11183973B1
公开(公告)日：2021-11-23
申请号：US16989421
申请日：2020-08-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ajaypat Jain , Amitoj Singh , Xiaohua Yu , Tienyu Chang , Siu-Chuang Ivan Lu , Sang Won Son
Abstract: An electronic circuit and method are provided. The electronic circuit includes an in-phase (I)-quadrature (Q) amplifier including an I cascode branch and a Q cascode branch, the IQ amplifier configured to receive a differential input and control signals, control, based on the control signals, gate voltages in the I cascode branch and gate voltages in the Q cascode branch, generate an I output signal with the I cascode branch, and generate a Q output signal with the Q cascode branch, and a quadrature coupler configured to perform quadrature summation of the I output signal and the Q output signal and generate a final phase shifted output.
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