公开(公告)号：US20220399864A1

公开(公告)日：2022-12-15

申请号：US17746856

申请日：2022-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Omar Abdulmonem Mohamed Elsayed ,  Venumadhav Bhagavatula ,  Tienyu Chang ,  Siu-Chuang Ivan Lu ,  Sangwon Son

IPC: H03G3/30 ,  H03F3/45 ,  H03K5/01

Abstract: A variable gain amplifier includes a first transconductor circuit coupled to a first input terminal, a first output terminal, and a second output terminal of the variable gain amplifier, the first transconductor circuit including: a plurality of positive coefficient transistors coupled to the first output terminal and configured to selectively conduct current in response to a first binary code, a plurality of negative coefficient transistors coupled to the second output terminal and configured to selectively conduct current in response to a second binary code, and a plurality of amplifying transistors, each having a gate electrode coupled to the first input terminal, a first electrode coupled to a ground reference, and a second electrode coupled to a pair of coefficient transistors including one of the plurality of positive coefficient transistors and one of the plurality of negative coefficient transistors.

公开(公告)号：US10044321B2

公开(公告)日：2018-08-07

申请号：US15277534

申请日：2016-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Venumadhav Bhagavatula ,  Siuchuang Ivan Lu ,  Sang Won Son

IPC: H03D7/14

Abstract: An apparatus and a method. The apparatus includes passive mixers, wherein each of the passive mixers includes a first input for receiving BBI, a second input for receiving BBI, a third input for receiving BBQ, a fourth input for receiving BBQ, a fifth input for receiving a first clock signal with a unique phase shift within one of the passive mixers, a sixth input for receiving a second clock signal with a unique phase shift within one of the passive mixers, a seventh input for receiving a third clock signal with a unique phase shift within one of the passive mixers, an eighth input for receiving a fourth clock signal with a unique phase shift within one of the passive mixers, and at least one output; and a voltage-domain vector summation array connected to the output of each of the passive mixers.

公开(公告)号：US20240235536A1

公开(公告)日：2024-07-11

申请号：US18313139

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd

Inventor： Samrat Dey ,  Venumadhav Bhagavatula ,  Siuchuang Ivan Lu ,  Sangwon Son

IPC: H03K5/01 ,  H01P5/00

CPC classification number: H03K5/01 ,  H01P5/00 ,  H03K2005/00286

Abstract: A method, a phase shifter, and a user equipment (UE) are disclosed for transmitting and receiving signals in a phased array. The method includes receiving, by a balun of a phase shifter, a transmission single-ended input signal at a single-ended side of the balun and generating a transmission differential input signal at a differential side of the balun, generating, by a differential quadrature coupler of the phase shifter, a transmission in-phase signal and a transmission quadrature signal, based on the transmission differential input signal, and combining, by a differential attenuator of the phase shifter, the transmission in-phase signal and the transmission quadrature signal into a differential phase-shifted output signal.

公开(公告)号：US12074575B2

公开(公告)日：2024-08-27

申请号：US17746856

申请日：2022-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Omar Abdulmonem Mohamed Elsayed ,  Venumadhav Bhagavatula ,  Tienyu Chang ,  Siu-Chuang Ivan Lu ,  Sangwon Son

IPC: H03G3/30 ,  H03F3/45 ,  H03K5/00 ,  H03K5/01

CPC classification number: H03G3/30 ,  H03F3/45475 ,  H03K5/01 ,  H03G2201/103 ,  H03K2005/00286

Abstract: A variable gain amplifier includes a first transconductor circuit coupled to a first input terminal, a first output terminal, and a second output terminal of the variable gain amplifier, the first transconductor circuit including: a plurality of positive coefficient transistors coupled to the first output terminal and configured to selectively conduct current in response to a first binary code, a plurality of negative coefficient transistors coupled to the second output terminal and configured to selectively conduct current in response to a second binary code, and a plurality of amplifying transistors, each having a gate electrode coupled to the first input terminal, a first electrode coupled to a ground reference, and a second electrode coupled to a pair of coefficient transistors including one of the plurality of positive coefficient transistors and one of the plurality of negative coefficient transistors.

公开(公告)号：US12113301B2

公开(公告)日：2024-10-08

申请号：US17235415

申请日：2021-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Venumadhav Bhagavatula ,  Siu-Chuang Ivan Lu ,  Sang Won Son

IPC: H04B1/44 ,  H01Q5/307 ,  H01Q5/42 ,  H01Q5/50 ,  H04B1/00

CPC classification number: H01Q5/42 ,  H01Q5/307 ,  H01Q5/50 ,  H04B1/005 ,  H04B1/44

Abstract: A radio frequency integrated circuit (RFIC) and method of communication are provided. The RFIC includes phased-locked loop (PLL) and data stream circuitry and a plurality of tiles in communication with the PLL and data stream circuitry. The plurality of tiles includes comprising at least one tile for each frequency band of the RFIC. The plurality of tiles are configured to communicate a data stream signal between tiles in a cascading sequence. Each tile of the plurality of tiles includes a plurality of up/down conversion mixers for converting the data stream signal between an intermediate frequency (IF) and a radio frequency (RF). Each tile also includes a plurality of front end (FE) elements, each in communication with a corresponding antenna and an up/down conversion mixer of the plurality of up/down conversion mixers.

公开(公告)号：US10312861B2

公开(公告)日：2019-06-04

申请号：US15608254

申请日：2017-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Venumadhav Bhagavatula ,  Sriramkumar Venugopalan ,  Siddharth Seth ,  Siuchuang Ivan Lu ,  Sang Won Son

IPC: H03K5/00 ,  H03D7/12 ,  H03H11/28 ,  H03H11/32 ,  H03K17/691 ,  H03K17/693 ,  H03D7/14

Abstract: An apparatus and method are provided. The apparatus includes a multiplexer, including first, second, and third inputs, and an output; a first transistor, including a gate connected to the multiplexer, and first and second terminals; a first variable capacitor, including a first terminal connected to the first transistor, a second terminal, and an input; a first inductor, including a first terminal connected to the first transistor, and a second terminal connected to the second terminal of the first variable capacitor; a second transistor, including a gate connected to the output of the multiplexer, a first terminal, and a second terminal connected to the second terminal of the first inductor; a second inductor mutually coupled to the first inductor, including a first and second terminals; and a balun-bias switch, including first, second, and third inputs, and an output connected to the second terminal of the second inductor.

公开(公告)号：US09923529B2

公开(公告)日：2018-03-20

申请号：US15137349

申请日：2016-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siddharth Seth ,  Venumadhav Bhagavatula ,  Ivan Lu ,  Sang Won Son

IPC: H04W72/04 ,  H03F3/24 ,  H03F3/19 ,  H04L5/22 ,  H04B1/04 ,  H04W72/12

CPC classification number: H03F3/245 ,  H03F3/19 ,  H03F3/217 ,  H03F3/24 ,  H03F2200/451 ,  H04B1/0475 ,  H04B2001/0408 ,  H04L5/22 ,  H04W72/1263

Abstract: Apparatuses, systems, and methods for a digital power amplifier (DPA) to generate a monotonic and linear ramp-up and ramp-down for a time division multiple access (TDMA) slot transmission are described. In one aspect, a monotonic and linear amplitude-to-control input code relationship model is generated for the DPA and stored. When the DPA needs to generate a ramp-up or ramp-down, the stored monotonic and linear amplitude-to-control input code relationship model is used to shape the input control code before it is input into the DPA. A new monotonic and linear amplitude-to-control input code relationship model may be generated and stored if the operating conditions change. The apparatuses, systems, and methods described herein may be applied to a multi-standard broadband modem chip capable of 2G transmission.

公开(公告)号：US09667228B2

公开(公告)日：2017-05-30

申请号：US15065433

申请日：2016-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Venumadhav Bhagavatula ,  Sriramkumar Venugopalan ,  Siddharth Seth ,  Siuchuang Ivan Lu ,  Sang Won Son

IPC: H03H7/40 ,  H03H11/28 ,  H03H11/32 ,  H03K17/691 ,  H03K17/693 ,  H03D7/12

CPC classification number: H03D7/125 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03H11/28 ,  H03H11/32 ,  H03K17/691 ,  H03K17/693

Abstract: An apparatus and method are provided. The apparatus includes a multiplexer, including a first input, a second input, a third input, and an output; a first transistor, including a gate, a first terminal, and a second terminal; a first variable capacitor, including a first terminal, a second terminal, and an input; a first inductor, including a first terminal and a second terminal; a second transistor, including a gate, a first terminal, and a second terminal; a second inductor mutually coupled to the first inductor, including a first terminal and a second terminal; a balun-bias switch, including a first input, a second input, a third input, and an output; a second capacitor, including a first terminal, and a second terminal; and a port-switch, including a first input, a second input, a third input, and an output.