Band switching balun
    5.
    发明授权

    公开(公告)号:US11799504B2

    公开(公告)日:2023-10-24

    申请号:US17585480

    申请日:2022-01-26

    CPC classification number: H04B1/006 H03D7/1425 H04B1/123 H04B1/44

    Abstract: A band-switching network includes a dual-band balun and a switch network. The dual-band balun includes a first output and a second output. The switch network includes a first switch and a second switch in which an input to the first switch is coupled to the first output and an input to the second switch is coupled to the second balanced output. The dual-band balun further includes a primary coil, a first secondary coil and a second secondary coil in which the first secondary coil is coupled to the first balanced output and the second secondary coil is coupled to the second balanced output. In one embodiment, the primary coil and the first secondary coil are coupled by a first coupling factor k1, and the primary coil and the second secondary coil are coupled by a second coupling factor k2 that is different from the first coupling factor k1.

    Low noise amplifier and method for carrier aggregation and non-carrier aggregation
    6.
    发明授权
    Low noise amplifier and method for carrier aggregation and non-carrier aggregation 有权
    低噪声放大器和载波聚合和非载波聚合方法

    公开(公告)号:US09362975B2

    公开(公告)日:2016-06-07

    申请号:US14519810

    申请日:2014-10-21

    Abstract: A low noise amplifier for carrier aggregation and non-carrier aggregation is provided. The low noise amplifier includes a plurality of symmetrical half circuits, a plurality of bias circuits, where each of the plurality of bias circuits is connected to one of the plurality of symmetrical half circuits, a plurality of capacitors, where each of the plurality of capacitors is connected to one of the plurality of symmetrical half circuits for Alternating Current (AC) coupling an RF signal containing at least one component carrier, and a control logic circuit connected to each of the plurality of symmetrical half circuits for configuring the low noise amplifier to process one component carrier or a plurality of component carriers.

    Abstract translation: 提供了用于载波聚合和非载波聚合的低噪声放大器。 低噪声放大器包括多个对称半电路,多个偏置电路,其中多个偏置电路中的每一个连接到多个对称半电路中的一个,多个电容器,其中多个电容器 连接到用于耦合包含至少一个分量载波的RF信号的交流电(AC)中的一个对称半电路以及连接到多个对称半电路中的每一个的控制逻辑电路,用于将低噪声放大器配置为 处理一个分量载体或多个分量载体。

    Method of synchronizing the H and V phase in a dual-polarized phased array system

    公开(公告)号:US11916641B2

    公开(公告)日:2024-02-27

    申请号:US17695460

    申请日:2022-03-15

    CPC classification number: H04B7/10 H04B1/38 H04B1/50 H04B17/101

    Abstract: A communication device, including a plurality of transceiver modules; a storage configured to store calibration information; and at least one processor configured to: generate a first dual-polarized RF signal by controlling a first transceiver module to generate a first RF signal based on the calibration information; measure, by a second transceiver module, a first signal power of the first dual-polarized RF signal; adjust a parameter of the first transceiver module, and generate a second dual-polarized RF signal by controlling the first transceiver module to generate a second RF signal based on the adjusted parameter; measure, by the second transceiver module, a second signal power of the second dual-polarized RF signal; and generate an aligned dual-polarized RF signal by controlling the plurality of transceiver modules to generate a plurality of RF signals based on a result of a comparison between the first signal power and the second signal power.

    METHOD AND CIRCUIT FOR POWER CONSUMPTION REDUCTION IN ACTIVE PHASE SHIFTERS

    公开(公告)号:US20220085763A1

    公开(公告)日:2022-03-17

    申请号:US17532340

    申请日:2021-11-22

    Abstract: An electronic circuit and method are provided. The electronic circuit includes an amplifier including first cascode branch and a second cascode branch, the amplifier being configured to receive a differential input and control signals, control gate voltages in the first cascode branch and gate voltages in the second cascode branch, generate a first output signal with the first cascode branch, and generate a second output signal with the second cascode branch, and a coupler configured to perform a summation of the first output signal and the second output signal, and generate a final phase shifted output, wherein the first cascode branch or the second cascode branch includes a first cascode arm and a second cascode arm.

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