公开(公告)号：US09735170B2

公开(公告)日：2017-08-15

申请号：US14973182

申请日：2015-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H01L29/788 ,  H01L27/11582 ,  H01L27/11578 ,  H01L23/498 ,  H01L27/11575 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/408 ,  H01L29/4234 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US20140327067A1

公开(公告)日：2014-11-06

申请号：US14331582

申请日：2014-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soodoo Chae ,  Myoungbum Lee

IPC: H01L27/115

CPC classification number: H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, and a plurality of gate electrodes. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicular to the semiconductor substrate. The gate electrodes include a first gate electrode and a second gate electrode. The first gate electrode is disposed on the memory cell region to intersect the active pillars. The second gate electrode is disposed on the contact region, connected to the first gate electrode and comprising metal material.

Abstract translation: 三维非易失性存储器件及其制造方法包括半导体衬底，多个有源柱和多个栅电极。 半导体衬底包括存储单元区域和接触区域。 活性柱在垂直于半导体衬底的存储单元区域中延伸。 栅电极包括第一栅电极和第二栅电极。 第一栅电极设置在存储单元区域上以与有源支柱相交。 第二栅电极设置在接触区域上，连接到第一栅电极并且包括金属材料。