公开(公告)号：US20240164103A1

公开(公告)日：2024-05-16

申请号：US18418720

申请日：2024-01-22

申请人： Samsung Electronics Co., Ltd.

发明人： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC分类号： H10B43/27 ,  H01L23/498 ,  H01L23/522 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50

CPC分类号： H10B43/27 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L29/408 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H01L2924/0002

摘要： A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US20220059567A1

公开(公告)日：2022-02-24

申请号：US17517137

申请日：2021-11-02

申请人： Samsung Electronics Co., Ltd.

发明人： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC分类号： H01L27/11582 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L27/11578 ,  H01L23/522 ,  H01L27/11575 ,  H01L27/11565 ,  H01L23/498

摘要： A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US09245839B2

公开(公告)日：2016-01-26

申请号：US14027599

申请日：2013-09-16

申请人： Samsung Electronics Co., Ltd.

发明人： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC分类号： H01L29/792 ,  H01L23/498 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/408 ,  H01L29/4234 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US10763222B2

公开(公告)日：2020-09-01

申请号：US15352890

申请日：2016-11-16

申请人： Samsung Electronics Co., Ltd.

发明人： Jaeho Jeong ,  Sunyoung Kim ,  Jang-Gn Yun ,  Hoosung Cho ,  Sunghoi Hur

IPC分类号： H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

摘要： Three-dimensional (3D) semiconductor devices may be provided. A 3D semiconductor device may include a substrate including a chip region and a scribe line region, a cell array structure including memory cells three-dimensionally arranged on the chip region of the substrate, a stack structure disposed on the scribe line region of the substrate and including first layers and second layers that are vertically and alternately stacked, and a plurality of vertical structures extending along a vertical direction that is perpendicular to a top surface of the substrate and penetrating the stack structure.

公开(公告)号：US20240155840A1

公开(公告)日：2024-05-09

申请号：US18416095

申请日：2024-01-18

申请人： Samsung Electronics Co., Ltd.

发明人： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC分类号： H10B43/27 ,  H01L23/498 ,  H01L23/522 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50

CPC分类号： H10B43/27 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L29/408 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H01L2924/0002

摘要： A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US20220037355A1

公开(公告)日：2022-02-03

申请号：US17497417

申请日：2021-10-08

申请人： Samsung Electronics Co., Ltd.

发明人： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC分类号： H01L27/11582 ,  H01L27/11578 ,  H01L27/11575 ,  H01L23/498 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522 ,  H01L27/11565

摘要： A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US10546872B2

公开(公告)日：2020-01-28

申请号：US15634597

申请日：2017-06-27

申请人： Samsung Electronics Co., Ltd.

发明人： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC分类号： H01L27/11582 ,  H01L27/11578 ,  H01L27/11575 ,  H01L23/498 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522 ,  H01L27/11565

摘要： A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US09735170B2

公开(公告)日：2017-08-15

申请号：US14973182

申请日：2015-12-17

申请人： Samsung Electronics Co., Ltd.

发明人： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC分类号： H01L29/788 ,  H01L27/11582 ,  H01L27/11578 ,  H01L23/498 ,  H01L27/11575 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423

CPC分类号： H01L27/11582 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/408 ,  H01L29/4234 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US09219072B2

公开(公告)日：2015-12-22

申请号：US14548557

申请日：2014-11-20

申请人： Samsung Electronics Co., Ltd

发明人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

IPC分类号： H01L27/115 ,  H01L23/522

CPC分类号： H01L27/11578 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11582

摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

摘要翻译： 具有三维结构的非易失性存储装置。 非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸，以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。

公开(公告)号：US20220359566A1

公开(公告)日：2022-11-10

申请号：US17870037

申请日：2022-07-21

申请人： Samsung Electronics Co., Ltd.

发明人： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC分类号： H01L27/11582 ,  H01L27/11578 ,  H01L27/11575 ,  H01L23/498 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522 ,  H01L27/11565

摘要： A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.