公开(公告)号：US11195566B2

公开(公告)日：2021-12-07

申请号：US16946217

申请日：2020-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C8/18 ,  G11C7/10 ,  G11C8/10 ,  G11C29/50 ,  G11C29/02

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US20190324854A1

公开(公告)日：2019-10-24

申请号：US16389080

申请日：2019-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-hwan Park ,  Tae-young Oh ,  Hyung-joon Chi ,  Kyung-soo Ha ,  Hyong-ryol Hwang

IPC: G06F11/10 ,  G11C7/22

Abstract: A memory device includes: a first memory bank and a second memory bank; a control logic configured to receive a command and control an internal operation of the memory device; and an error correction code (ECC) circuit configured to retain in a latch circuit first read data read from the first memory bank in response to a first masked write (MWR) command for the first memory bank based on a latch control signal from the control logic, generate a first parity from data in which the first read data retained in the latch circuit is merged with first write data corresponding to the first MWR command in response to a first write control signal received from the control logic, and control an ECC operation to retain in the latch circuit second read data read from the second memory bank based on the latch control signal.

公开(公告)号：US20170117033A1

公开(公告)日：2017-04-27

申请号：US15224683

申请日：2016-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-yeon Doo ,  Tae-young Oh ,  Cheol Kim ,  Geun-tae Park

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/40626 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4091

Abstract: Provided is a method of refreshing a memory device by controlling a self-refresh cycle according to temperature. In the method, first self-refresh and second self-refresh are performed according to inner temperature of the memory device and a self-refresh cycle is controlled such that an all-bank-refresh (ABR) operation is not performed simultaneously with the start of the second self-refresh. The ABR operation is performed at the start of third self-refresh when the sum of a section of the first self-refresh in which the ABR operation is not performed and a section of the second self-refresh in which the ABR operation is not performed corresponds to a self-refresh cycle.

公开(公告)号：US09324458B2

公开(公告)日：2016-04-26

申请号：US14096824

申请日：2013-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-joong Kim ,  Tae-young Oh

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/07

CPC classification number: G11C29/76 ,  G06F11/073

Abstract: Provided are a memory controller, a memory system including the memory controller, and an operating method performed by the memory controller. The operating method includes operations of queuing a first command in a first queue, detecting a fail of a first address that corresponds to the first command, when the first address is determined as a fail address, queuing a second address and a second command in the first queue, wherein the second address is obtained by remapping the first address and the second command corresponds to the second address, and outputting the second command and the second address from the first queue.

Abstract translation: 提供了存储器控制器，包括存储器控制器的存储器系统和由存储器控制器执行的操作方法。 操作方法包括在第一队列中排队第一命令，检测到与第一命令相对应的第一地址的失败的操作，当第一地址被确定为故障地址时，排队第二地址和第二命令中的第二命令 第一队列，其中通过重新映射第一地址获得第二地址，并且第二命令对应于第二地址，并且从第一队列输出第二命令和第二地址。