公开(公告)号：US20230317128A1

公开(公告)日：2023-10-05

申请号：US18332325

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C8/10 ,  G11C29/50 ,  G11C29/02

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/18 ,  G11C8/10 ,  G11C7/1084 ,  G11C29/50012 ,  G11C29/022 ,  G11C29/028 ,  G11C29/023 ,  G11C7/1072 ,  G11C2207/2272 ,  G11C2207/2254

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US10720197B2

公开(公告)日：2020-07-21

申请号：US16196777

申请日：2018-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C8/10 ,  G11C29/50 ,  G11C29/02

Abstract: There are provided, a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US20190304517A1

公开(公告)日：2019-10-03

申请号：US16363077

申请日：2019-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Kyung-soo Ha ,  Young-Soo Sohn ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Jin-Hoon Jang ,  Yeon-Kyu Choi ,  Seok-Hun Hyun

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US20250149076A1

公开(公告)日：2025-05-08

申请号：US19018469

申请日：2025-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US20250124959A1

公开(公告)日：2025-04-17

申请号：US19002120

申请日：2024-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US11715504B2

公开(公告)日：2023-08-01

申请号：US17518888

申请日：2021-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C8/18 ,  G11C29/50 ,  G11C7/10 ,  G11C8/10 ,  G11C29/02

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C8/10 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C7/1072 ,  G11C2207/2254 ,  G11C2207/2272

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US09805787B2

公开(公告)日：2017-10-31

申请号：US15334082

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-soo Ha

IPC: G11C5/06 ,  G11C11/4094 ,  G11C7/12 ,  G11C11/4096 ,  H03K19/00

CPC classification number: G11C11/4094 ,  G11C7/1057 ,  G11C7/12 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/021 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/16 ,  G11C29/20 ,  G11C29/24 ,  G11C29/46 ,  G11C2029/0409 ,  G11C2029/5002 ,  G11C2029/5004 ,  G11C2207/2254 ,  H03K19/0005

Abstract: A memory device may include a calibration circuit configured to perform a calibration operation of generating a pull-up control code and a pull-down control code in a calibration mode, and in a stress applying mode, turn on at least one of each of first and second transistor units to apply stress, and an on-die termination (ODT)/off-chip driver (OCD) circuit, a resistance value of the ODT/OCD circuit being adjusted in response to at least one of the pull-up control code and the pull-down control code. The calibration circuit includes a pull-up control code generator including the first transistor unit and a pull-down control code generator including the second transistor unit.

公开(公告)号：US12217823B2

公开(公告)日：2025-02-04

申请号：US18332325

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US11195566B2

公开(公告)日：2021-12-07

申请号：US16946217

申请日：2020-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C8/18 ,  G11C7/10 ,  G11C8/10 ,  G11C29/50 ,  G11C29/02

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US20190324854A1

公开(公告)日：2019-10-24

申请号：US16389080

申请日：2019-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-hwan Park ,  Tae-young Oh ,  Hyung-joon Chi ,  Kyung-soo Ha ,  Hyong-ryol Hwang

IPC: G06F11/10 ,  G11C7/22

Abstract: A memory device includes: a first memory bank and a second memory bank; a control logic configured to receive a command and control an internal operation of the memory device; and an error correction code (ECC) circuit configured to retain in a latch circuit first read data read from the first memory bank in response to a first masked write (MWR) command for the first memory bank based on a latch control signal from the control logic, generate a first parity from data in which the first read data retained in the latch circuit is merged with first write data corresponding to the first MWR command in response to a first write control signal received from the control logic, and control an ECC operation to retain in the latch circuit second read data read from the second memory bank based on the latch control signal.