公开(公告)号：US10720197B2

公开(公告)日：2020-07-21

申请号：US16196777

申请日：2018-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C8/10 ,  G11C29/50 ,  G11C29/02

Abstract: There are provided, a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US11715504B2

公开(公告)日：2023-08-01

申请号：US17518888

申请日：2021-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C8/18 ,  G11C29/50 ,  G11C7/10 ,  G11C8/10 ,  G11C29/02

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C8/10 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C7/1072 ,  G11C2207/2254 ,  G11C2207/2272

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US20230317128A1

公开(公告)日：2023-10-05

申请号：US18332325

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C8/10 ,  G11C29/50 ,  G11C29/02

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/18 ,  G11C8/10 ,  G11C7/1084 ,  G11C29/50012 ,  G11C29/022 ,  G11C29/028 ,  G11C29/023 ,  G11C7/1072 ,  G11C2207/2272 ,  G11C2207/2254

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US20250149076A1

公开(公告)日：2025-05-08

申请号：US19018469

申请日：2025-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US20250124959A1

公开(公告)日：2025-04-17

申请号：US19002120

申请日：2024-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US12217823B2

公开(公告)日：2025-02-04

申请号：US18332325

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US11195566B2

公开(公告)日：2021-12-07

申请号：US16946217

申请日：2020-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C8/18 ,  G11C7/10 ,  G11C8/10 ,  G11C29/50 ,  G11C29/02

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.