公开(公告)号：US10714473B2

公开(公告)日：2020-07-14

申请号：US16671478

申请日：2019-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hyun Song ,  Yoon Suk Kim ,  Kyu Baik Chang ,  Ui Hui Kwon ,  Yo Han Kim ,  Jong Chol Kim ,  Chang Wook Jeong

IPC: H01L27/088 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

公开(公告)号：US20200066720A1

公开(公告)日：2020-02-27

申请号：US16671478

申请日：2019-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hyun Song ,  Yoon Suk Kim ,  Kyu Baik Chang ,  Ui Hui Kwon ,  Yo Han Kim ,  Jong Chol Kim ,  Chang Wook Jeong

IPC: H01L27/088 ,  H01L29/06 ,  H01L27/02 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

公开(公告)号：US20180121587A1

公开(公告)日：2018-05-03

申请号：US15645227

申请日：2017-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Udit MONGA ,  Jong Wook Jeon ,  Ken Machida ,  Ui Hui Kwon

IPC: G06F17/50 ,  G06F17/18

Abstract: A soft error rate (SER) associated with a design of a semiconductor circuit may be predicted based on implementing a simulation associated with the design. The simulation may include generating a simulation environment based on information indicating the design, performing a particle strike simulation based on the simulation environment to generate charge deposition information, and calculating a collected charge quantity from the charge deposition information. A determination may be made whether the SER predicted based on the collected charge quantity at least meets a threshold. The design may be modified, and the simulation repeated, if the predicted SER value meets a threshold value. A semiconductor circuit may be manufactured based on the design if the predicted SER value is less than the threshold value.