公开(公告)号：US10049728B2

公开(公告)日：2018-08-14

申请号：US15611274

申请日：2017-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoonki Kim ,  Jonghoon Jung ,  Yongho Kim

IPC: G11C11/419

Abstract: A semiconductor memory device including: a first transistor connected between a first node and ground, the first transistor having a gate connected to a second node; a second transistor connected between the second node and ground, the second transistor having a gate connected to the first node; a third transistor connected between first and third nodes, the third transistor having a gate connected to the second node; a fourth transistor connected between second and fourth nodes, the fourth transistor having a gate connected to the first node; a fifth transistor connected between the first node and bit line, the fifth transistor having a gate connected to a word line; a sixth transistor connected between the second node and complementary bit line, the sixth transistor having a gate connected to the word line; and a circuit to reduce a gate-source voltage of the third or fourth transistor in a write operation.

公开(公告)号：US12272665B2

公开(公告)日：2025-04-08

申请号：US18378166

申请日：2023-10-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongho Kim

IPC: H01L23/00

Abstract: A semiconductor package includes: a first semiconductor device including a first pad and a first metal bump structure on the first pad; and a second semiconductor device on the first semiconductor device, and including a third pad and a second metal bump structure on the third pad, wherein the first and second metal bump structures are bonded to each other to electrically connect the first and second semiconductor devices to each other. Each of the first and second metal bumps structures includes first to third metal patterns. The first to third metal patterns of the first metal bump structure are on the first pad. The first to third metal patterns of the second metal bump structure are on the third pad. The first and third metal patterns include a first metal having a first coefficient of thermal expansion less than that of a second metal of the second metal pattern.

公开(公告)号：US11694994B2

公开(公告)日：2023-07-04

申请号：US16865649

申请日：2020-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongho Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L25/0657 ,  H01L23/293 ,  H01L24/13 ,  H01L2924/00

Abstract: A semiconductor chip stack includes first and second semiconductor chips. The first chip includes a first semiconductor substrate having an active surface and an inactive surface, a first insulating layer formed on the inactive surface, and first pads formed in the first insulating layer. The second semiconductor chip includes a second semiconductor substrate having an active surface and an inactive surface, a second insulating layer formed on the active surface, second pads formed in the second insulating layer, a polymer layer formed on the second insulating layer, UBM patterns buried in the polymer layer; and buried solders formed on the UBM patterns, respectively, and buried in the polymer layer. A lower surface of the buried solders is coplanar with that of the polymer layer, the buried solders contact the first pads, respectively, at a contact surface, and a cross-sectional area of the buried solders is greatest on the contact surface.

公开(公告)号：USD973081S1

公开(公告)日：2022-12-20

申请号：US29778630

申请日：2021-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Jangwoo Lee ,  Yongho Kim ,  Seoeun Park

公开(公告)号：US11223497B2

公开(公告)日：2022-01-11

申请号：US16578753

申请日：2019-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeseul Hong ,  Yongho Kim ,  Sunah Kim ,  Boram Lee ,  Taeksoo Chun

IPC: H04L12/28

Abstract: A method and apparatus capable of forwarding notification or information related to a function, generated from a given device, to a user through a device near (or in proximity to) the user by interworking a plurality of electronic devices, are provided. An electronic device includes a communication interface and a processor. The processor is configured to obtain a first message related to notification from an external device, identify a target electronic device for notification output based on the location of a user and notification output performance of each of a plurality of electronic devices capable of communication with the electronic device, and transmit a second message related to the notification to the target electronic device so that the identified target electronic device outputs the notification.

公开(公告)号：US20180075929A1

公开(公告)日：2018-03-15

申请号：US15699412

申请日：2017-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HOONKI KIM ,  Yongho Kim ,  Changnam Park ,  Taejoong Song ,  Woojin Rim ,  Jonghoom Jung

IPC: G11C29/00 ,  G11C5/02 ,  G11C7/10 ,  G11C29/26

CPC classification number: G11C29/702 ,  G11C5/025 ,  G11C7/1012 ,  G11C29/26 ,  G11C29/76 ,  G11C29/838

Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of columns including a normal column and a redundancy column for repairing the normal column, a plurality of peripheral logic circuits including a normal peripheral logic circuit and a redundancy peripheral logic circuit for repairing the normal peripheral logic circuit, and a first path selection logic circuit configured to form first paths between the plurality of columns and the plurality of peripheral logic circuits, based on at least one defect from among a defect in at least one of the plurality of columns or a defect in at least one of the plurality of peripheral logic circuits.