Method for responding to user utterance and electronic device for supporting same

    公开(公告)号:US11631406B2

    公开(公告)日:2023-04-18

    申请号:US16960764

    申请日:2019-01-21

    Abstract: In an embodiment of the disclosure, disclosed is an electronic device including a communication module, a microphone, a first and a second wake-up recognition module, a memory, and a processor. The processor is configured to receive a first user utterance through the microphone, recognize the first user utterance based on at least one of the first or the second wake-up recognition module, when the recognized first user utterance includes specified at least one first trigger information, record at least part of the first user utterance by activating the recording function, transmit recorded data to an external device, and receive at least one of second user utterance information, which is predicted to occur at a time after the function of the speech recognition service is activated by the first wake-up recognition module, or at least one response information associated with the second user utterance from the external device.

    Trilayer bonding bump structure for semiconductor package

    公开(公告)号:US11798908B2

    公开(公告)日:2023-10-24

    申请号:US17215131

    申请日:2021-03-29

    Inventor: Yongho Kim

    Abstract: A semiconductor package includes: a first semiconductor device including a first pad and a first metal bump structure on the first pad; and a second semiconductor device on the first semiconductor device, and including a third pad and a second metal bump structure on the third pad, wherein the first and second metal bump structures are bonded to each other to electrically connect the first and second semiconductor devices to each other. Each of the first and second metal bumps structures includes first to third metal patterns. The first to third metal patterns of the first metal bump structure are on the first pad. The first to third metal patterns of the second metal bump structure are on the third pad. The first and third metal patterns include a first metal having a first coefficient of thermal expansion less than that of a second metal of the second metal pattern.

    SEMICONDUCTOR CHIP STACK STRUCTURE, SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20210066251A1

    公开(公告)日:2021-03-04

    申请号:US16865649

    申请日:2020-05-04

    Inventor: Yongho Kim

    Abstract: A semiconductor chip stack includes first and second semiconductor chips. The first chip includes a first semiconductor substrate having an active surface and an inactive surface, a first insulating layer formed on the inactive surface, and first pads formed in the first insulating layer. The second semiconductor chip includes a second semiconductor substrate having an active surface and an inactive surface, a second insulating layer formed on the active surface, second pads formed in the second insulating layer, a polymer layer formed on the second insulating layer, UBM patterns buried in the polymer layer; and buried solders formed on the UBM patterns, respectively, and buried in the polymer layer. A lower surface of the buried solders is coplanar with that of the polymer layer, the buried solders contact the first pads, respectively, at a contact surface, and a cross-sectional area of the buried solders is greatest on the contact surface.

    Semiconductor device
    9.
    发明授权

    公开(公告)号:US10163838B2

    公开(公告)日:2018-12-25

    申请号:US15499272

    申请日:2017-04-27

    Abstract: A semiconductor device includes a semiconductor chip, pads provided on the semiconductor chip, and insulating patterns provided on the semiconductor chip. The insulating patterns having openings exposing the pads, and conductive patterns are provided in the openings and coupled to the pads. When viewed in a plan view, two opposite ends of the pads are spaced apart from the conductive patterns and two opposite ends of the conductive patterns are spaced apart from the pads. Additionally, when viewed in a plan view, the conductive patterns include a first conductive pattern whose length is parallel to a first direction and a second conductive pattern whose length is parallel to a second direction. The first and second directions are oblique to each other.

Patent Agency Ranking