公开(公告)号：US20220342833A1

公开(公告)日：2022-10-27

申请号：US17858506

申请日：2022-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsun PARK ,  Jun-Woo JANG ,  Yoojin KIM ,  Channoh KIM

IPC: G06F13/16

Abstract: A data transmission method for a convolution operation, and a convolution operation apparatus including a fetcher that includes a loader, at least one sender, a buffer controller, and a reuse buffer. The method includes loading, by the loader, input data of an input feature map according to a loading order, based on input data stored in the reuse buffer, a shape of a kernel to be used for a convolution operation, and two-dimensional (2D) zero-value information of weights of the kernel; storing, by the buffer controller, the loaded input data in the reuse buffer of an address cyclically assigned according to the loading order; and selecting, by each of the at least one sender, input data corresponding to each output data of a convolution operation among the input data stored in the reuse buffer, based on one-dimensional (1D) zero-value information of the weights, and outputting the selected input data.

公开(公告)号：US20220164289A1

公开(公告)日：2022-05-26

申请号：US17317339

申请日：2021-05-11

Applicant: Samsung Electronics Co., Ltd

Inventor： Yoojin KIM ,  Channoh KIM ,  Hyun Sun PARK ,  Sehwan LEE ,  Jun-Woo JANG

IPC: G06F12/0862 ,  G06F12/0804

Abstract: A computing method and device with data sharing re provided. The method includes loading, by a loader, input data of an input feature map stored in a memory in loading units according to a loading order, storing, by a buffer controller, the loaded input data in a reuse buffer of an address rotationally allocated according to the loading order, and transmitting, by each of a plurality of senders, to an executer respective input data corresponding to each output data of respective convolution operations among the input data stored in the reuse buffer, wherein portions of the transmitted respective input data overlap other.

公开(公告)号：US20220024815A1

公开(公告)日：2022-01-27

申请号：US17311390

申请日：2019-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sejin KIM ,  Jinchoul PARK ,  Junsang PARK ,  Wanju SHIN ,  Hwanju JEON ,  Younggoo KANG ,  Yoojin KIM ,  Gijea PARK ,  Yunhui CHO

IPC: C03C17/34 ,  H05K5/03 ,  G02B5/00

Abstract: An electronic device according to various embodiments of the disclosure may include a housing including a first plate forming an outer face. The first plate may include a glass plate including a first surface outwardly facing the housing and a second surface inwardly facing the housing, a coating layer including an anti-reflection coating and/or an anti-finger coating above the first surface while forming the outer face, a first layer formed between the first surface of the first glass plate and the coating layer, having a first thickness, and including a first inorganic material, a second layer formed between the first layer and the coating layer, having a second thickness, and including a second inorganic material different from the first inorganic material, a third layer formed between the second layer and the coating layer, having a third thickness thicker than each of the first thickness and the second thickness, and including a third inorganic material, and an opaque layer formed on the second surface. Various other embodiments may also be possible.

公开(公告)号：US20210117781A1

公开(公告)日：2021-04-22

申请号：US16857588

申请日：2020-04-24

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Yoojin KIM ,  Soonhoi HA ,  Donghyun KANG ,  Jintaek KANG

IPC: G06N3/08 ,  G06N3/04

Abstract: A processor-implemented neural network method includes: generating a bit vector based on whether each of a plurality of input activations within a neural network is 0; merging the bit vector into the input activations such that bit values within the neural network included in the bit vector are most significant bits (MSBs) of multi bit expressions of the input activations; merging the bit vector into weights such that the bit values included in the bit vector are MSBs of multi bit expressions of the weights; sorting the input activations and the weights based on bits corresponding to the MSBs; and implementing the neural network, including performing operations between the sorted input activations and the sorted weights.