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    Image sensor, pixel, and method of operating the pixel
    11.
    发明授权
    Image sensor, pixel, and method of operating the pixel 有权

    公开(公告)号：US11665444B2

    公开(公告)日：2023-05-30

    申请号：US17561050

    申请日：2021-12-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyungmin Kim ,  Changeun Kang ,  Hoyong Na ,  Jihun Shin ,  Youngtae Jang ,  Youngkyun Jeong

    IPC: H04N25/59 ,  H04N25/58 ,  H04N25/75

    CPC classification number: H04N25/59 ,  H04N25/58 ,  H04N25/75

    Abstract: An image sensor includes a pixel array, in which a plurality of pixels are arranged, and a row driver for controlling the plurality of pixels. Each of the plurality of pixels includes a first photodiode, a second photodiode having a larger light-receiving area than the first photodiode, a first floating diffusion node in which charges generated by the first photodiode are stored, a first capacitor connected to the first floating diffusion node, and a capacitor control transistor having one end connected in series to the first capacitor. For each of the plurality of pixels, the row driver adjusts capacitance of the first floating diffusion node by using the capacitor control transistor for each of a plurality of preset operation modes during a readout period of the first photodiode.

    Memory device, operating method of the memory device, and memory system including the same
    14.
    发明授权
    Memory device, operating method of the memory device, and memory system including the same 有权

    公开(公告)号：US12210777B2

    公开(公告)日：2025-01-28

    申请号：US18242250

    申请日：2023-09-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyungmin Kim ,  Byongmo Moon

    IPC: G06F3/06

    Abstract: In some embodiments, a memory device includes a data sampler configured to sample a data signal based on a write data strobe signal, a measuring circuit configured to measure a temperature-based delay variation and a voltage-based delay variation of a transfer path of the write data strobe signal, a storage circuit configured to store a first coefficient code regulating a reference-based delay variation on the transfer path, a temperature sensor configured to sense the temperature of the transfer path, a monitoring circuit configured to generate a second coefficient code by comparing the sensed temperature, the temperature-based delay variation, the voltage-based delay variation, and the reference-based delay variation with each other, a reference voltage generator configured to generate a reference voltage, a voltage regulator configured to generate a regulation voltage, and a write data strobe signal transfer circuit configured to transfer the write data strobe signal to the data sampler.

    IMAGE SENSOR HAVING REDUCED PARASITIC CAPACITANCE
    19.
    发明申请
    IMAGE SENSOR HAVING REDUCED PARASITIC CAPACITANCE 有权

    公开(公告)号：US20210120200A1

    公开(公告)日：2021-04-22

    申请号：US16890422

    申请日：2020-06-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunyool Kang ,  Yongjun Cho ,  Yunhwan Jung ,  Heesung Chae ,  Kyungmin Kim ,  Haesick Sul ,  Sukki Yoon

    IPC: H04N5/3745 ,  H01L27/146

    Abstract: An image sensor, including a pixel array including a plurality of pixels connected to row lines extending in a first direction and column lines extending in a second direction intersecting the first direction; a ramp voltage generator configured to output a ramp voltage; a sampling circuit including a plurality of comparators, each comparator of the plurality of comparators having a first input terminal connected to a column of the column lines and a second input terminal configured to receive the ramp voltage; and an analog-to-digital converter configured to convert an output of the plurality of comparators to a digital signal, wherein the plurality of comparators include a first comparator connected to a first column line, and a second comparator connected to a second column line adjacent to the first column line in the first direction, wherein each of the first comparator and the second comparator includes a first transistor and a second transistor disposed sequentially in the second direction, and wherein a gap between the first transistor of the first comparator and the second transistor of the first comparator is different from a gap between the first transistor of the second comparator and the second transistor of the second comparator.

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