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    IMAGE SENSOR
    1.
    发明申请
    IMAGE SENSOR 有权

    公开(公告)号：US20220078362A1

    公开(公告)日：2022-03-10

    申请号：US17459045

    申请日：2021-08-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yunhwan Jung ,  Hyeokjong Lee ,  Sunyool Kang ,  Kyungmin Kim ,  Yunhong Kim ,  Ingyeong Shin

    IPC: H04N5/355 ,  H04N5/378 ,  H04N5/3745

    Abstract: An image sensor includes a pixel configured to operate in a high conversion gain (HCG) mode and a low conversion gain (LCG) mode during a readout period, and a correlated double sampling (CDS) circuit configured to generate a comparison signal based on a ramp signal and a pixel voltage received from the pixel, wherein the CDS circuit includes a comparator configured to: receive the pixel voltage through a first input node, receive the ramp signal through a second input node based on an LCG reset signal or an LCG image signal being received as the pixel voltage, and receive the ramp signal through a third input node based on an HCG reset signal or an HCG image signal being received as the pixel voltage; and compare the ramp signal to the pixel voltage, and output the comparison signal corresponding to a comparison result.

    ANALOG-TO-DIGITAL CIRCUIT AND OPERATION METHOD THEREOF
    2.
    发明申请
    ANALOG-TO-DIGITAL CIRCUIT AND OPERATION METHOD THEREOF 有权

    公开(公告)号：US20250038760A1

    公开(公告)日：2025-01-30

    申请号：US18596913

    申请日：2024-03-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yunhong Kim ,  Heesung Chae ,  Keunyeol Park ,  Ingyeong Shin ,  Moo Young Kim

    IPC: H03M1/34 ,  H04N25/77

    Abstract: Disclosed is an analog-to-digital converter (ADC) circuit for digitizing a pixel signal into a digital signal of positive integer (N) bits. The ADC includes a ramp generator, a clock, a comparator, and a counter. A system clock signal allows the ramp generator to generate a ramp signal and the clock generator to generate first to N-th clock signals. The comparator generates a comparison signal based on a comparison of the pixel signal, received from a pixel array, and the ramp signal. The counter includes an additional latch circuit and first to N-th latch circuits. The additional latch circuit generates an additional binary signal based on the system clock signal and the comparison signal, and the first to N-th latch circuits generate first to N-th latch signals based on the comparison signal and corresponding clock signal.

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