公开(公告)号：US20240348943A1

公开(公告)日：2024-10-17

申请号：US18630604

申请日：2024-04-09

申请人： Sony Semiconductor Solutions Corporation

发明人： Luonghung Asakura ,  Hiromu Kato

IPC分类号： H04N25/616 ,  H04N25/75 ,  H04N25/772

CPC分类号： H04N25/616 ,  H04N25/75 ,  H04N25/772

摘要： Solid-state imaging elements are disclosed. In one example, an upstream circuit block generates a predetermined reset level and a plurality of signal levels each corresponding to an exposure amount, and causes capacitive elements, different from each other, to hold them. A selection circuit sequentially performs control to connect the capacitive element in which the reset level is held to a predetermined downstream node, control to disconnect capacitive elements from the downstream node, and control to connect the capacitive element in which any of the plurality of signal levels is held to the downstream node. A downstream reset transistor initializes a level of the downstream node when the capacitive elements are disconnected from the downstream node. A downstream circuit sequentially reads the reset level and the plurality of signal levels via the downstream node.

公开(公告)号：US20240284075A1

公开(公告)日：2024-08-22

申请号：US18292726

申请日：2022-01-31

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION

发明人： HIDEKI NAGANUMA ,  TAKUYA TOYOFUKU

IPC分类号： H04N25/78 ,  H04N25/616 ,  H04N25/673 ,  H04N25/771

CPC分类号： H04N25/78 ,  H04N25/616 ,  H04N25/673 ,  H04N25/771

摘要： To improve the image quality in a solid-state imaging element that performs differential amplification. Each of a plurality of reference pixels is provided with a reference-side amplifier transistor that supplies a reference current according to a predetermined reference potential. Each of a plurality of readout pixel circuits is provided with a readout-side amplifier transistor that supplies from a drain to a source a signal current according to a difference between a potential of a gate and the reference potential. Further, in a potential difference generation unit, a plurality of source follower transistors are arranged for each of columns of the readout pixel circuits, each source follower transistor controlling a potential difference between the gate and the drain to a predetermined value when the potential of the gate and the reference potential are initialized.

公开(公告)号：US20240205555A1

公开(公告)日：2024-06-20

申请号：US18068638

申请日：2022-12-20

申请人： CAELESTE CVBA

发明人： Bart DIERICKX

IPC分类号： H04N25/50 ,  H04N23/95 ,  H04N25/76 ,  H04N25/767 ,  H04N25/78

CPC分类号： H04N25/50 ,  H04N23/95 ,  H04N25/767 ,  H04N25/7795 ,  H04N25/78 ,  H04N25/616

摘要： A solid-state image sensor with quasi-global shutter function and a method of operating the same. A row control unit of the image sensor is configured to determine exceptional pixel rows for which a pre-scheduled global exposure control pulse would fully or partially coincide with a sequentially applied readout control pulse that is selecting a number of pixel rows of the pixel array to be read out. The pre-scheduled global exposure control pulse is applied simultaneously to all but the exceptional pixel rows and delayed and/or advanced versions of the exposure control pulse are applied to the exceptional pixel rows.

公开(公告)号：US20240187752A1

公开(公告)日：2024-06-06

申请号：US18550180

申请日：2022-01-13

申请人： Sony Semiconductor Solutions Corporation

发明人： LuongHung Asakura

IPC分类号： H04N25/616 ,  H04N25/532 ,  H04N25/766 ,  H04N25/78

CPC分类号： H04N25/616 ,  H04N25/532 ,  H04N25/766 ,  H04N25/78

摘要： To improve image quality in a solid-state imaging element that simultaneously performs exposure in all pixels.
The solid-state imaging element includes a predetermined number of capacitive elements, a pre-stage circuit, a selection circuit, a post-stage circuit, and a vertical scanning circuit. The pre-stage circuit generates a predetermined reset level and a signal level corresponding to an exposure amount, and causes each of the capacitive elements to hold a corresponding one of the reset level and the signal level. In the selection circuit, a selection transistor that opens and closes a path between one end of each capacitive element and a predetermined node is arranged. The post-stage circuit sequentially reads the reset level and the signal level via the node. The vertical scanning circuit performs control to lower the potential of the one end when the reset level and the signal level are held.

公开(公告)号：US11950005B2

公开(公告)日：2024-04-02

申请号：US17868349

申请日：2022-07-19

申请人： Nuvoton Technology Corporation Japan

发明人： Hiroyuki Amikawa ,  Makoto Ikuma ,  Kazutoshi Onozawa

IPC分类号： H04N25/59 ,  H04N25/616 ,  H04N25/75 ,  H04N25/65 ,  H04N25/677 ,  H04N25/771

CPC分类号： H04N25/616 ,  H04N25/59 ,  H04N25/75 ,  H04N25/65 ,  H04N25/677 ,  H04N25/771

摘要： A solid-state imaging device includes: a photoelectric conversion element that is disposed on a semiconductor substrate and generates signal charges by photoelectric conversion; a first diffusion layer that holds signal charges transferred from the photoelectric conversion element; a capacitive element that holds signal charges overflowing from the photoelectric conversion element; an amplifier transistor that outputs a signal according to the signal charges in the first diffusion layer; a first contact that is connected to the first diffusion layer; a second contact that is connected to a gate of the amplifier transistor; and a first wire that connects the first contact and the second contact. A shortest distance between the semiconductor substrate and the first wire is less than a shortest distance between the semiconductor substrate and the capacitive element.

公开(公告)号：US20240080592A1

公开(公告)日：2024-03-07

申请号：US18453345

申请日：2023-08-22

申请人： CANON KABUSHIKI KAISHA

发明人： KEITA MASUDA ,  ATSUSHI SHIMADA ,  YASUHIRO KATO ,  KEISUKE TAKAHASHI ,  TAKESHI SHIMADA

IPC分类号： H04N25/78 ,  H04N25/616 ,  H04N25/63 ,  H04N25/65 ,  H04N25/767

CPC分类号： H04N25/78 ,  H04N25/616 ,  H04N25/63 ,  H04N25/65 ,  H04N25/767

摘要： A photoelectric conversion apparatus includes a pixel array having a plurality of column signal lines which are divided into a plurality of groups, a readout circuit configured to read out signals from the pixel array via the plurality of column signal lines. A holding unit includes one first region and a plurality of second regions. A plurality of first correction values respectively corresponding to the plurality of columns are stored in the first region. Each second region is associated with a readout condition for reading signals from each pixel unit of the pixel array by the readout circuit, and a plurality of second correction values respectively corresponding to the plurality of groups are stored in each second region.

公开(公告)号：US20240064439A1

公开(公告)日：2024-02-22

申请号：US18499545

申请日：2023-11-01

申请人： CANON KABUSHIKI KAISHA

发明人： Hideo Kobayashi

IPC分类号： H04N25/772 ,  H04N25/616

CPC分类号： H04N25/772 ,  H04N25/616

摘要： A photoelectric conversion device comprising a pixel portion in which pixels each including a photoelectric converter are arranged, a sample/hold unit configured to sample a signal generated in the photoelectric converter via a vertical signal line and hold the signal, and a converter configured to perform an analog/digital conversion is provided. In the sample/hold unit, a first sample/hold circuit that samples a signal for when the photoelectric converter is reset and a second sample/hold circuit that samples a signal for when a photoelectric conversion operation is performed are connected to one vertical signal line. The pixel portion is arranged on a first substrate, a part of a group configured by the sample/hold unit and the converter is arranged on a second substrate, and another part of the group is arranged on a third substrate.

公开(公告)号：US11902678B2

公开(公告)日：2024-02-13

申请号：US18093705

申请日：2023-01-05

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION

发明人： Fumihiko Koga

IPC分类号： H04N25/616 ,  H01L27/146 ,  H04N23/10 ,  H04N25/65 ,  H04N25/67 ,  H04N25/68 ,  H04N25/70 ,  H04N25/76 ,  H04N25/772 ,  H04N25/778 ,  H10K39/32 ,  H04N25/13

CPC分类号： H04N25/616 ,  H01L27/1464 ,  H01L27/14612 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14647 ,  H01L27/14665 ,  H04N23/10 ,  H04N25/65 ,  H04N25/67 ,  H04N25/68 ,  H04N25/70 ,  H04N25/76 ,  H04N25/772 ,  H04N25/778 ,  H10K39/32 ,  H01L27/14621 ,  H01L27/14627 ,  H04N25/134

摘要： The present technology relates to a solid-state imaging device that can improve imaging quality by reducing variation in the voltage of a charge retention unit, a method of driving the solid-state imaging device, and an electronic apparatus. A first photoelectric conversion unit generates and accumulates signal charge by receiving light that has entered a pixel, and photoelectrically converting the light. A first charge retention unit retains the generated signal charge. A first output transistor outputs the signal charge in the first charge retention unit as a pixel signal, when the pixel is selected by the first select transistor. A first voltage control transistor controls the voltage of the output end of the first output transistor. The present technology can be applied to pixels in solid-state imaging devices, for example.

公开(公告)号：US20230345144A1

公开(公告)日：2023-10-26

申请号：US18040947

申请日：2021-06-29

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION

发明人： YOSHIO AWATANI ,  PAWANKUMAR PRADEEPKUMAR MOYADE

IPC分类号： H04N25/616 ,  H04N25/709 ,  H04N25/78 ,  H04N25/703 ,  H04N25/77

CPC分类号： H04N25/616 ,  H04N25/703 ,  H04N25/709 ,  H04N25/77 ,  H04N25/78 ,  H04N25/671

摘要： Provided is a solid-state imaging element provided with a comparator for each column, the solid-state imaging element improving the image quality of image data. The solid-state imaging element includes a first comparison element and a transistor. An input voltage related to the voltage of a vertical signal line is input to a source of the first comparison element, and the first comparison element outputs a drain voltage corresponding to the gate-source voltage from a drain. A signal corresponding to the voltage of the vertical signal line is input to a gate of the transistor, and a source of the transistor is connected to the drain of the first comparison element.

公开(公告)号：US20230319431A1

公开(公告)日：2023-10-05

申请号：US18329169

申请日：2023-06-05

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yunhwan JUNG ,  Hyeokjong LEE ,  Sunyool Kang ,  Kyungmin Kim ,  Yunhong KIM ,  Ingyeong SHIN

IPC分类号： H04N25/585 ,  H04N25/75 ,  H04N25/77 ,  H04N25/616 ,  H04N25/709 ,  H04N25/78

CPC分类号： H04N25/585 ,  H04N25/75 ,  H04N25/77 ,  H04N25/616 ,  H04N25/709 ,  H04N25/78

摘要： An image sensor includes a pixel configured to operate in a high conversion gain (HCG) mode and a low conversion gain (LCG) mode during a readout period, and a correlated double sampling (CDS) circuit configured to generate a comparison signal based on a ramp signal and a pixel voltage received from the pixel, wherein the CDS circuit includes a comparator configured to: receive the pixel voltage through a first input node, receive the ramp signal through a second input node based on an LCG reset signal or an LCG image signal being received as the pixel voltage, and receive the ramp signal through a third input node based on an HCG reset signal or an HCG image signal being received as the pixel voltage; and compare the ramp signal to the pixel voltage, and output the comparison signal corresponding to a comparison result.