公开(公告)号：US11769813B2

公开(公告)日：2023-09-26

申请号：US18046518

申请日：2022-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dong Won Kim ,  Woo Seok Park ,  Keun Hwi Cho ,  Sung Gi Hur

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/4236 ,  H01L29/78696

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

公开(公告)号：US11482606B2

公开(公告)日：2022-10-25

申请号：US17209290

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dong Won Kim ,  Woo Seok Park ,  Keun Hwi Cho ,  Sung Gi Hur

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

公开(公告)号：US10896955B2

公开(公告)日：2021-01-19

申请号：US16401347

申请日：2019-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangmook Lim ,  Sang Su Kim ,  Woo Seok Park ,  Sung Gi Hur

IPC: H01L27/01 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/786 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L27/092 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, an active region disposed on the substrate and extending in a first direction, a device isolation layer adjacent to the active region, a gate structure disposed in the active region, the gate structure extending in a second direction crossing the first direction, and covering a portion of the device isolation layer, a gate separation pattern contacting an end of the gate structure, and an impurity region disposed below the gate separation pattern and on the device isolation layer.

公开(公告)号：US10177150B2

公开(公告)日：2019-01-08

申请号：US15615643

申请日：2017-06-06

Applicant: Samsung Electronics Co. Ltd.

Inventor： Junggil Yang ,  Sangsu Kim ,  TaeYong Kwon ,  Sung Gi Hur

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/306 ,  H01L29/423 ,  H01L29/10

Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.

公开(公告)号：US20160268394A1

公开(公告)日：2016-09-15

申请号：US15165931

申请日：2016-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gi Hur ,  TaeYong Kwon ,  Sangsu Kim ,  Jungdal Choi

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L29/66553 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7849

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.